DSP56F807PY80 查看數據表（PDF） - Freescale Semiconductor
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DSP56F807PY80 Datasheet PDF : 60 Pages
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56F807 General Description
• Up to 40 MIPS at 80MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• Hardware DO and REP loops
• MCU-friendly instruction set supports both DSP
and controller functions: MAC, bit manipulation
unit, 14 addressing modes
• 60K × 16-bit words (120KB) Program Flash
• 2K × 16-bit words (4KB) Program RAM
• 8K × 16-bit words (16KB) Data Flash
• 4K × 16-bit words (8KB) Data RAM
• 2K × 16-bit words (4KB) Boot Flash
• Up to 64K × 16- bit words (128KB) each of external
Program and Data memory
• Two 6 channel PWM Modules
• Four 4 channel, 12-bit ADCs
• Two Quadrature Decoders
• CAN 2.0 B Module
• Two Serial Communication Interfaces (SCIs)
• Serial Peripheral Interface (SPI)
• Up to four General Purpose Quad Timers
• JTAG/OnCETM port for debugging
• 14 Dedicated and 18 Shared GPIO lines
• 160-pin LQFP or 160 MAPBGA Packages
6
PWM Outputs
Current Sense Inputs
3
Fault Inputs
4
6
PWM Outputs
3
Current Sense Inputs
Fault Inputs
4
4
A/D1 ADCA
4
A/D2 VREF
4
A/D1 ADCB
A/D2
4
VREF2
Quadrature
Decoder 0
4
/Quad Timer
PWMA
PWMB
Interrupt
Controller
Quadrature
Decoder 1
Program Memory
4
/Quad Timer B
61440 x 16 Flash
2048 x 16 SRAM
Quad Timer C
2
Boot Flash
Quad Timer D
2048 x 16 Flash
4
/ Alt Func
CAN 2.0A/B
Data Memory
2
SCI0
8192 x 16 Flash
4096 x 16 SRAM
or
2
GPIO
SCI1
or
2
GPIO
COP/
Watchdog
SPI
Applica-
or
tion-Specific
4
GPIO
Memory &
Dedicated
GPIO
Peripherals
14
RSTO
EXTBOOT
RESET IRQB
IRQA
6
JTAG/
OnCE
Port
VPP VCAPC VDD VSS VDDA
2
8
10* 3
VSSA
3
Digital Reg Analog Reg
Low Voltage
Supervisor
Program Controller
and
Hardware Looping Unit
Address
Generation
Unit
Data ALU
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Bit
Manipulation
Unit
••
PAB
PDB
•
XDB2
• CGDB
•
•
XAB1
XAB2
•
•
INTERRUPT
IPBB
CONTROLS CONTROLS
16
16
COP RESET
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
IPBus Bridge
(IPBB)
16-Bit
56800
Core
PLL
Clock Gen
CLKO
XTAL
EXTAL
External 6
Address Bus
A[00:05]
A[06:15] or
External
Bus
Interface
Unit
Switch
External
Data Bus
Switch
GPIO-E2:E3 &
10 GPIO-A0:A7
D[00:15]
16
PS Select
Bus
DS Select
Control
WR Enable
RD Enable
*includes TCS pin which is reserved for factory use and is tied to VSS
56F807 Block Diagram
56F807 Technical Data Technical Data, Rev. 16
Freescale Semiconductor
3
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