DSP56F826PB 查看數據表（PDF） - Freescale Semiconductor

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DSP56F826PB

16-bit Digital Signal Controllers

Freescale Semiconductor 

Signals and Package Information

Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)

Signal

Name

XTAL

Pin No.

62

Type

Output

Description

Crystal Oscillator Output—This output connects the internal crystal oscillator

output to an external crystal or ceramic resonator. If an external clock source

over 4MHz is used, XTAL must be used as the input and EXTAL connected to

VSS. For more information, please refer to Section 3.6.3.

(CLOCKIN)

Input

External Clock Input—This input should be asserted when using an external

clock or ceramic resonator.

CLKO

65

Output

Clock Output—This pin outputs a buffered clock signal. By programming the

CLKO Select Register (CLKOSR), the user can select between outputting a

version of the signal applied to XTAL and a version of the device master clock at

the output of the PLL. The clock frequency on this pin can be disabled by

programming the CLKO Select Register (CLKOSR).

A0

24

(GPIOE0)

Output

Address Bus—A0–A7 specify the address for external program or data memory

accesses.

A1

(GPIOE1)

A2

(GPIOE2)

23

Input/Output Port E GPIO—These eight General Purpose I/O (GPIO) pins can be individually

programmed as input or output pins.

22

After reset, the default state is Address Bus.

A3

21

(GPIOE3)

A4

18

(GPIOE4)

A5

17

(GPIOE5)

A6

16

(GPIOE6)

A7

15

(GPIOE7)

56F826 Technical Data, Rev. 14

Freescale Semiconductor

11

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