General Description
Features
• 16-bit CPU12
– Upward compatible with M68HC11 instruction set
– Interrupt stacking and programmer’s model identical to
M68HC11
– 20-bit ALU
– Instruction queue
– Enhanced indexed addressing
• Multiplexed bus
– Single chip or expanded
– 16 address/16 data wide or 16 address/8 data narrow mode
• Memory
– 128K byte flash EEPROM, made of four 32K byte modules
with 8K bytes protected BOOT section in each module
(68HC912DG128 only)
– 128K byte ROM (68HC12DG128 only)
– 2K byte EEPROM
– 8K byte RAM, made of two 4K byte modules with Vstby in each
module.
• Analog-to-digital converters
– 2 times x 8-channels, 10-bit resolution
• Two 1M bit per second, CAN 2.0 A, B software compatible
modules each with:
– Two receive and three transmit buffers
– Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or
8 x 8 bit
– Four separate interrupt channels for Rx, Tx, error and wake-up
– Low-pass filter wake-up function
– Loop-back for self test operation
68HC(9)12DG128 Rev 1.0
12
General Description
2-gen
MOTOROLA