73K222AL-IH/F 查看數據表（PDF） - Teridian Semiconductor Corporation
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73K222AL-IH/F Datasheet PDF : 27 Pages
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73K222AL
V.22, V.21, Bell 212A, 103
Single-Chip Modem
DATA SHEET
CONTROL REGISTER 0 (continued)
D7
CR0
000 MODUL.
OPTION
BIT NO.
D7
D6
D5
D4
D3
D2
0
TRANSMIT TRANSMIT TRANSMIT TRANSMIT
MODE 3
MODE 2
MODE 1
MODE 0
NAME
CONDITION DESCRIPTION
Modulation
Option
D7 D5 D4
0 0X
Selects:
DPSK mode at 1200 bit/s.
1 0X
DPSK mode at 600 bit/s.
0 11
1 11
FSK Bell 103 mode.
FSK CCITT V.21 mode.
X = Don’t care
D1
TRANSMIT
ENABLE
D0
ANSWER/
ORIGINATE
CONTROL REGISTER 1
D7
D6
CR1 TRANSMIT TRANSMIT
001 PATTERN PATTERN
1
0
BIT NO.
NAME
D1, D0
Test Mode
D2
Reset
D3
CLK Control
(Clock Control)
D5
D4
D3
D2
D1
D0
ENABLE
DETECT
INTER.
BYPASS
CLK
SCRAMB CONTROL
RESET
TEST
MODE
1
TEST
MODE
0
CONDITION
D1 D0
00
01
10
11
DESCRIPTION
Selects normal operating mode.
Analog loopback mode. Loops the transmitted analog
signal back to the receiver, and causes the receiver to
use the same center frequency as the transmitter. To
squelch the TXA pin, transmit enable must be forced
low.
Selects remote digital loopback. Received data is looped
back to transmit data internally, and RXD is forced to a
mark. Data on TXD is ignored.
Selects local digital loopback. Internally loops TXD back
to RXD and continues to transmit carrier from TXA pin.
0
Selects normal operation.
1
Resets modem to power down state. All control
register bits (CR0, CR1, Tone) are reset to zero. The
output of the CLK pin will be set to the crystal frequency.
0
Selects 11.0592 MHz crystal echo output at CLK pin.
1
Selects 16 X the data rate, output at CLK pin in DPSK
modes only.
Page: 10 of 27
© 2007 TERIDIAN Semiconductor Corporation
Rev 6.1
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