73K222AL-IHR 查看數據表（PDF） - Teridian Semiconductor Corporation

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73K222AL-IHR

V.22, V.21, Bell 212A, 103 Single-Chip Modem

Teridian Semiconductor Corporation 

DESCRIPTION (continued)

This device supports V.22 (except mode v) and V. 21

modes of operation, allowing both synchronous and

asynchronous communications. Test features such as

analog loop, digital loop, and remote digital loopback are

supported. Internal pattern generators are also included for

self-testing. The 73K222AL is designed to appear to the

systems designer as a microprocessor peripheral, and will

easily interface with popular one-chip microprocessors

(80C51 typical) for control of modem functions through its 8-

bit multiplexed address/data bus or serial control bus. An

ALE control line simplifies address demultiplexing. Data

communications occurs through a separate serial port only.

The 73K222AL is ideal for use in either free standing or

integral system modem products where full-duplex 1200

bit/s data communications over the 2-wire switched

telephone network is desired. Its high functionality, low

power consumption and efficient packaging simplify

design requirements and increase system reliability. A

complete modem requires only the addition of the phone

line interface, a control microprocessor, and RS-232 level

converter for a typical system. The 73K222AL is part of

TERIDIAN Semiconductor Corporation's K-Series family of

pin and function compatible single-chip modem products.

These devices allow systems to be configured for higher

speeds and Bell or CCITT operation with only a single

component change.

OPERATION

ASYNCHRONOUS MODE

Data transmission for the DPSK mode requires that data

ultimately be transmitted in a synchronous fashion. The

73K222AL includes ASYNC/SYNC and SYNC/ASYNC

converters, which delete or insert stop bits in order to

transmit data within a ±0.01% rate. In asynchronous mode

the serial data comes from the TXD pin into the

ASYNC/SYNC converter. The ASYNC/SYNC converter

accepts the data provided on the TXD pin which normally

must be 1200 or 600 bit/s +1.0%, -2.5%. The converter will

then insert or delete stop bits in order to output a signal,

which is 1200, or 600 bit/s ± 0.01% (± 0.01% is required

synchronous data rate accuracy).

The serial data stream from the ASYNC/SYNC

converter is passed through the data scrambler and

onto the analog modulator. The data scrambler can be

bypassed under processor control when unscrambled

data must be transmitted. The ASYNC/SYNC

converter and the data scrambler are bypassed in all

FSK modes. If serial input data contains a break signal

through one character (including start and stop bits)

the break will be extended to at least 2 times N + 3 bits

73K222AL

V.22, V.21, Bell 212A, 103

Single-Chip Modem

DATA SHEET

long (where N is the number of transmitted

bits/character).

Serial data from the demodulator is passed first

through the data descrambler and then through

the SYNC/ASYNC converter. The SYNC/ASYNC

convertor will reinsert any deleted stop bits and

transmit output data at an intra-character rate (bit-

to-bit timing) of no greater than 1219 bit/s. An

incoming break signal (low through two

characters) will be passed through without

incorrectly inserting a stop bit.

The SYNC/ASYNC converter also has an

extended overspeed mode, which allows selection

of an overspeed range of either +1% or +2.3%. In

the extended overspeed mode, stop bits are

output at 7/8 the normal width.

SYNCHRONOUS MODE

The CCITT V.22 standard defines synchronous

operation at 600 and 1200 bit/s. The Bell 212A

standard defines synchronous operation only at

1200 bit/s. Operation is similar to that of the

asynchronous mode except that data must be

synchronized to a provided clock and no variation

in data transfer rate is allowable. Serial input data

appearing at TXD must be valid on the rising edge

of TXCLK.

TXCLK is an internally derived signal in internal mode

and is connected internally to the RXCLK pin in slave

mode. Receive data at the RXD pin is clocked out on

the falling edge of RXCLK. The ASYNCH/SYNCH

converter is bypassed when synchronous mode is

selected and data is transmitted out at the same rate

as it is input.

DPSK MODULATOR/DEMODULATOR

The 73K222AL modulates a serial bit stream into

di-bit pairs that are represented by four possible

phase shifts as prescribed by the Bell 212A or

V.22 standards. The baseband signal is then

filtered to reduce intersymbol interference on the

bandlimited 2-wire telephone line. Transmission

occurs using either a 1200 Hz (originate mode) or

2400 Hz carrier (answer mode). Demodulation is

the reverse of the modulation process, with the

incoming analog signal eventually decoded into di-

bits and converted back to a serial bit stream. The

demodulator also recovers the clock, which was

encoded into the analog signal during modulation.

Demodulation occurs using either a 1200 Hz

carrier (answer mode or ALB originate mode) or a

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© 2007 TERIDIAN Semiconductor Corporation

Rev 6.1

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