73K222AL-IH/F 查看數據表（PDF） - Teridian Semiconductor Corporation
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73K222AL-IH/F Datasheet PDF : 27 Pages
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73K222AL
V.22, V.21, Bell 212A, 103
Single-Chip Modem
DATA SHEET
PIN DESCRIPTION (continued)
DTE USER
NAME
EXCLK
RXCLK
RXD
TXCLK
TXD
28-PIN
19
23
22
18
21
TYPE
I
O
O/
Weak
Pull -up
O
I
DESCRIPTION
External Clock. This signal is used in synchronous transmission
when the external timing option has been selected. In the external
timing mode the rising edge of EXCLK is used to strobe synchronous
DPSK transmit data applied to on the TXD pin. Also used for serial
control interface.
Receive Clock. The falling edge of this clock output is coincident with
the transitions in the serial received data output. The rising edge of
RXCLK can be used to latch the valid output data. RXCLK will be
valid as long as a carrier is present.
Received Data Output. Serial receive data is available on this pin.
The data is always valid on the rising edge of RXCLK when in
synchronous mode. RXD will output constant marks if no carrier is
detected.
Transmit Clock. This signal is used in synchronous transmission to
latch serial input data on the TXD pin. Data must be provided so that
valid data is available on the rising edge of the TXCLK. The transmit
clock is derived from different sources depending upon the
synchronization mode selection. In Internal Mode the clock is
generated internally. In External Mode TXCLK is phase locked to the
EXCLK pin. In Slave Mode TXCLK is phase locked to the RXCLK
pin. TXCLK is always active.
Transmit Data Input. Serial data for transmission is applied on this pin.
In synchronous modes, the data must be valid on the rising edge of the
TXCLK clock. In asynchronous modes (1200/600 bit/s or 300 baud)
no clocking is necessary. DPSK data must be 1200/600 bit/s +1%,
-2.5% or +2.3%, -2.5 % in extended overspeed mode.
ANALOG INTERFACE AND OSCILLATOR
RXA
TXA
XTL1
XTL2
27
I Received modulated analog signal input from the telephone line
interface.
16
O Transmit analog output to the telephone line interface.
2
I These pins are for the internal crystal oscillator requiring a 11.0592 MHz
3
I parallel mode crystal. Load capacitors should be connected from XTL1
and XTL2 to Ground. XTL2 can also be driven from an external clock.
Page: 6 of 27
© 2007 TERIDIAN Semiconductor Corporation
Rev 6.1
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