73K222AL-IHR/F 查看數據表（PDF） - Teridian Semiconductor Corporation
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73K222AL-IHR/F Datasheet PDF : 27 Pages
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REGISTER DESCRIPTIONS
Four 8-bit internal registers are accessible for control
and status monitoring. The registers are accessed in
read or write operations by addressing the A0, A1
and A2 address lines in serial mode, or the AD0,
AD1 and AD2 lines in parallel mode. In parallel
mode the address lines are latched by ALE. Register
CR0 controls the method by which data is
transferred over the phone line. CR1 controls the
interface between the microprocessor and the
REGISTER BIT SUMMARY
73K222AL
V.22, V.21, Bell 212A, 103
Single-Chip Modem
DATA SHEET
73K222AL internal state. DR is a detect register
which provides an indication of monitored
modem status conditions. TR, the tone control
register, controls the DTMF generator, answer
and guard tones and RXD output gate used in
the modem initial connect sequence. All
registers are read/write except for DR, which is
read only. Register control and status bits are
identified below:
ADDRESS
REGISTER
AD2 - AD0
D7
D6
CONTROL
REGISTER CR0
000
M O D U L AT IO N
O P T IO N
0
0
CONTROL
REGISTER CR1
001
1
T R AN S M IT
PATTERN
1
T R AN S M IT
PATTERN
0
DETECT
REGISTER DR
010
X
X
D5
T R AN SM IT
MODE
3
ENABLE
DETECT
IN T E R R U P T
RECEIVE
DATA
DATA BIT NUMBER
D4
D3
T R AN S M IT
MODE
2
T R AN SM IT
MODE
1
BYPASS
SCRAMBLER
CLK
CONTROL
UNSCR.
MARKS
CARRIER
DETECT
D2
T R AN S M IT
MODE
0
RESET
ANSWER
TONE
D1
T R AN SM IT
ENABLE
TEST
MODE
1
CALL
PROGRESS
D0
ANSWER/
O R IG IN AT E
TEST
MODE
0
LONG
LOOP
TONE
CONTROL
TR
011
R EG IST ER
CONTROL
REGISTER CR2
100
2
CONTROL
REGISTER CR3
101
3
ID
REGISTER
ID
110
RXD
OUTPUT
CONTROL
X
T R AN S M IT
GUARD
TONE
X
T R AN SM IT
ANSWER
TONE
X
T R AN S M IT
DTMF
DTMF3
DTMF2
DTMF1/
OVERSPEED
DTMF0/
GUARD/
ANS TONE
THESE REGISTER LOCATIONS ARE RESERVED FOR
X
X
X
X
USE WITH OTHER K-SERIES FAMILY MEMBERS
X
ID
ID
ID
ID
X
X
X
X
NOTE: When a register containing reserved control
bits is written into, the reserved bits must be
programmed as 0's.
X = Undefined, mask in software
Page: 7 of 27
© 2007 TERIDIAN Semiconductor Corporation
Rev 6.1
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