73K224BL-IHR/F 查看數據表（PDF） - Teridian Semiconductor Corporation
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73K224BL-IHR/F
Teridian Semiconductor Corporation
73K224BL-IHR/F Datasheet PDF : 33 Pages
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73K224BL
V.22bis, V.22, V.21, Bell 212A, 103
Single-Chip Modem w/ Integrated Hybrid
DATA SHEET
CONTROL REGISTER 0 (continued)
CR0
D7
D6
D5
D4
D3
D2
D1
D0
ADDR
000
BIT
D7
MODUL. MODUL.
OPTION TYPE 1
NAME
Modulation
Option
MODUL. TRANSMIT TRANSMIT TRANSMIT TRANSMIT
TYPE 0
MODE 2
MODE 1
MODE 0
ENABLE
ANSWER/
ORIGINATE
CONDITION DESCRIPTION
0
QAM selects 2400 bit/s. DPSK selects 1200 bit/s. FSK
selects 103 mode.
1
DPSK selects 600 bit/s.
FSK selects V.21 mode.
CONTROL REGISTER 1
CR1
D7
D6
D5
ADDR
001
TRANSMIT
PATTERN
1
TRANSMIT
PATTERN
0
ENABLE
DETECT
INTERRUPT
BIT
NAME
CONDITION
D0, D1
Test Mode
D1 D0
00
01
10
11
D2
Reset
0
1
D3
Clock Control
0
1
D4
BYPASS
SCRAMBLER
D3
CLOCK
CONTROL
D2
RESET
D1
TEST
MODE 1
DESCRIPTION
D0
TEST
MODE 0
Selects normal operating mode
Analog loopback mode. Loops the transmitted analog
signal back to the receiver, and causes the receiver to use
the same carrier frequency as the transmitter. To squelch
the TXA pin, transmit enable bit as well as Tone Register
bit D2 must be low.
Selects remote digital loopback. Received data is looped
back to transmit data internally, and RXD is forced to a
mark. Data on TXD is ignored.
Selects local digital loopback. Internally loops TXD back to
RXD and continues to transmit data carrier at TXA pin
Selects Normal Operations
Resets modem to power-down state. All Control Register
bits (CR0, CR1, CR2, CR3 and tone) are reset to zero
except CR3 bit D2. The output of the clock pin will be set
to the crystal frequency.
Selects 11.0592 MHz crystal echo output at CLK pin
Selects 16 times the data rate output at CLK pin in
DPSK/QAM modes only.
Page: 11 of 33
© 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
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