73M1903C-IMR/F 查看數據表（PDF） - Teridian Semiconductor Corporation
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73M1903C-IMR/F Datasheet PDF : 46 Pages
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73M1903C
Modem Analog Front End
DATA SHEET
CONTROL REGISTER MAP
The following Table 2 shows the map of addressable registers in the 73M1903C. Each register and its
bits are described in detail in the following sections.
Register
Name
Address Default
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2 BIT 1 BIT 0
CTRL
00h
08h ENFE SELTX2
TXBST(1:0)
TXDIS
RXG(1:0)
RXGAIN
TEST
01h
00h TMEN DIGLB ANALB INTLB CkoutEn RXPULL SPOS HC
DATA
02h
FFh GPIO7 GPIO 6 GPIO 5 GPIO 4 GPIO 3 GPIO 2 GPIO 1 GPIO 0
DIR
03h
FFh
DIR7 DIR6
DIR5
DIR4
DIR3
DIR2 DIR1 DIR0
Register04 04h
00h
Reserved
Register05 05h
00h
Reserved
REV
06h
60h
Rev(3:0)
FSDEn
Reserved
Register07 07h
00h
Reserved
PLL_PSEQ 08h
00h
Pseq(7:0)
PLL_RST 09h
0Ah
Prst(2:0)
Pdvsr(4:0)
PLL_KVCO 0Ah
22h
Ichp(3:0)
Reserved
Kvco(2:0)
PLL_DIV
0Bh
12h
-
Ndvsr(6:0)
PLL_SEQ 0Ch
00h
Nseq(7:0)
XTAL_BIAS 0Dh
C0h
Xtal(1:0)
Reserved
-
Nrst(2:0)
PLL_LOCK 0Eh
00H Frcvco PwdnPll LockDet
-
-
-
-
-
Note:
Register or bit names in bold underline denotes the READ ONLY bits and registers.
Register bits marked “-“ are not used. Writing any value to these bits won’t affect the operation.
Reserved are bits reserved for factory test purpose only. Do not attempt to write these locations to values
other than their default to prevent unexpected operation.
Register Bit notations used in this document are as follows.
- Registerxx: Register05 represents the register with Address 0x05
- BIT(s)NAME(MSB:LSB) ; Rev(3:0) represents 4 bits of Rev3, Rev2, Rev1 and Rev0.
-(RegisterAddress[BIT(s)]) ; (0X00[7]) represents Bit 7 of Register address 0x00, ENFE bit
(0X06[7:4]) represents Bit 7, Bit 6, Bit 5 and Bit4 of Register address 06, Rev(3:0).
Table 2: Register Map
Page: 11 of 46
© 2005-2008 TERIDIAN Semiconductor Corporation
Rev 4.3
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