73M1903C 查看數據表（PDF） - Teridian Semiconductor Corporation

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73M1903C

Modem Analog Front End

Teridian Semiconductor Corporation 

73M1903C

Modem Analog Front End

DATA SHEET

Register0E (PLL_LOCK): Address 0Eh

Reset State 00h

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

Frcvco PwdnPLL LockDet

-

-

BIT 2

-

BIT 1

-

BIT 0

-

Frcvco

PwdnPll

LockDet

(0X0E[7]) Force Vco as System clock Enable.

0 = Xtal oscillator as system clock.

1 = forces VCO as system clock. This bit is reset to ‘0’ upon reset, PwdnPll = 1 or ENFE = 0.

Both PwdnPll and ENFE are delayed coming out of digital section to keep PLL alive long

enough to transition the system clock to crystal clock when Frcvco is reset by PwdnPLL or

ENFE.

(0X0E[6]) PLL Power down Enable Please refer to the Table 4 Below.

1 = forces Power down of PLL analog section.

0: normal operation

(0X0E[5]) PLL Lock indicator. Read only.

1 = PLL locked

0 = PLL not locked.

ENFE

(Register00 bit7)

0

1

1

PwdnPll

(Register0E bit6)

X

0

1

PLL

PLL Power Off

PLL Power On

PLL Power Off

Table 4: PLL Power Down

Page: 16 of 46

© 2005-2008 TERIDIAN Semiconductor Corporation

Rev 4.3

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