73M1903C 查看數據表（PDF） - Teridian Semiconductor Corporation

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73M1903C

Modem Analog Front End

Teridian Semiconductor Corporation 

73M1903C

Modem Analog Front End

DATA SHEET

ANALOG I/O

Figure 7 shows the block diagram of the analog front end. The analog interface circuit uses differential

transmit and receive signals to and from the external circuitry.

The hybrid driver in the TERIDIAN 73M1903C IC is capable of connecting directly, but not limited to, a

transformer-based Direct Access Arrangement (DAA). The hybrid driver is capable of driving the DAA’s

line coupling transformer and load impedance. The hybrid drivers can also drive high impedance loads

without modification.

An on-chip band gap voltage is used to provide an internal voltage reference and bias currents for the

analog receive and transmit channels. The reference derived from the bandgap, nominally 1.25 Volts, is

multiplied to 1.36 Volts and output at the VREF pin. Several voltage references, nominally 1.25 Volts, are

used in the analog circuits. The band gap and reference circuits are disabled after a chip reset since the

ENFE (Register00 bit7) is reset to a default state of zero. When ENFE=0, the band gap voltage and the

analog bias currents are disabled. In this case all of the analog circuits are powered down and draw less

than 5 µA of current.

A clock generator (CKGN) is used to create all of the non-overlapping phase clocks needed for the time

sampled switched-capacitor circuits, ASDM, DAC1, and TLPF. The CKGN input is 2 times the

analog/digital interface sample rate or 3.072MHz clock for Fs=8kHz.

RXAP

RXAN

VBG

ANALOG

analb

MUX

Out

AMUX1

SE

L

Anti-Alias Filter

AAF

Analog

Sigma-Delta rbs

Modulator

ASDM

OPSR

BGAP

Bandgap

phase clocks (1.536 MHz)

CKGN

sck (3.072 MHz)

Clock Generator

phase clocks

(1.536 MHz)

DIGITAL

Decimating

Filter

1

15:0

MUX

DDEC

rbi

t

Clocks

PLL/

CLKDIV

Serial

Port

TXAP1

TXAN1

TXAP2

TXAN2

+-

Hybrid Drivers

SMFLT

Transmit

Low Pass

Filter

TLPF

Outp

DAC In tbs

DAC

Outn

1

MUX

1

tbit

Digital

Sigma-Delta

Modulator

15:0

DSDM

Page: 20 of 46

SFR

REGISTERS

Figure 7: Analog block diagram

© 2005-2008 TERIDIAN Semiconductor Corporation

Rev 4.3

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