73M2901CE-IGV/F 查看數據表（PDF） - Teridian Semiconductor Corporation

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73M2901CE-IGV/F

V.22bis Single Chip Modem

Teridian Semiconductor Corporation 

DS_2901CE_031

73M2901CE Data Sheet

RING is used to inform the 73M2901CE that the external DAA circuitry or ring energy detector has

detected a ring signal. It will go active when each “RING” message is sent on RXD.

In addition, sending any character on the TXD line also generates an internal interrupt.

1.5 Crystal Oscillator

The Teridian 73M2901CE single chip modem can use an external 11.0592 MHz reference clock or can

generate a clock using only a crystal and two capacitors. If an external clock is used, it should be applied

to the OSCIN pin.

1.5.1 Specifying a Crystal

The manufacturer of a crystal resonator verifies its frequency of oscillation in a test set-up, but to ensure

that the same frequency is obtained in the application, the circuit conditions must be the same.

The Teridian 73M2901CE modem requires a parallel mode (anti-resonant) crystal, the important

specifications of which are as follows:

Mode:

Frequency:

Frequency tolerance:

Temperature drift:

Load capacitance:

ESR:

Drive level:

Parallel (anti-resonant)

11.0592 MHz

±50 ppm at initial temperature

An additional ±50 ppm over full range

18 pF to 22 pF

75 Ω max

Less than 1 mW

The peak voltage level of the oscillator should be checked to assure it will not violate the maximum

voltage levels allowed on the oscillator pins. A resistor in series with the crystal can be used, if

necessary, to reduce the oscillator’s peak voltage levels.

Crystals with low ESRs may oscillate at higher than specified voltage levels.

1.6 Reset

A reset is accomplished by holding the RESET pin high. To ensure a proper power-on reset, the reset

pin must be held high for a minimum of 3 µs. At power on, the voltage at VPD, VPA, and RESET must

come up at the same time for a proper reset.

The signals DCD, CTS and DSR will be held inactive for 25 ms, acknowledging the reset operation, within

a 250 ms time window after the reset-triggering event. The 73M2901CE is ready for operation after the

250 ms window and/or after the signals DCD, CTS and DSR become active.

1.7 Asynchronous and Synchronous Serial Data Interface

The serial data interface consists of the TXD and RXD data paths (LSB shifted in and out first) and the

TXCLK and RXCLK serial synchronous clock outputs associated with the data pins; CTS/RTS flow

control; DCD, DSR and DTR. In asynchronous mode, the data is passed at the bit rate (tolerance is +1%,

-2.5%).

Rev. 3.4

5

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