ICS8431CM-01 查看數據表（PDF） - Integrated Circuit Systems
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ICS8431CM-01 Datasheet PDF : 11 Pages
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Integrated
Circuit
Systems, Inc.
ICS8431-01
200MHZ, LOW JITTER,
LVPECL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
The ICS8431-01 is a general purpose clock
,&6
frequency synthesizer for IA64/32 application and
HiPerClockS™ a member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS8431-01 consists of one independent low
bandwidth PLL timing channel. A 16.666MHz crystal is used
as the input to the on-chip oscillator. The M is configured to
produce a fixed output frequency of 200MHz.
Programmable features of the ICS8431-01 support four
operational modes. The four modes are spread spectrum
clocking (SSC), non-spread spectrum clock and two test
modes which are controlled by the SSC_CTL[1:0] pins. Un-
like other synthesizers, the ICS8431-01 can immediately
change spread-spectrum operation without having to reset
the device.
In SSC mode, the output clock is modulated in order to
achieve a reduction in EMI. In one of the PLL bypass test
modes, the PLL is disconnected as the source to the
differential output allowing an external source to be
connnected to the TEST_I/O pin. This is useful for in-
circuit testing and allows the differential output to be driven
at a lower frequency throughout the system clock tree. In the
other PLL bypass mode, the oscillator divider is used as the
source to both the M and the Fout divide by 2. This is useful
for characterizing the oscillator and internal dividers.
FEATURES
• Fully integrated PLL
• Differential 3.3V LVPECL output
• 200MHz output frequency
• 48% to 52% duty cycle
• Crystal oscillator interface
• Spread Spectrum Clocking (SSC) fixed at 1/2% modulation
for environments requiring ultra low EMI. Typical10dB EMI
reduction can be achieved with spread spectrum modulation
• LVTTL / LVCMOS control inputs
• PLL bypass modes supporting in-circuit testing and on-chip
functional block characterization
• 28 lead SOIC
• RMS cycle-to-cycle jitter of 2ps
• Typical cycle-to-cycle jitter of 18ps
• 0° to 85°C ambiant operating temperature
BLOCK DIAGRAM
XTAL1
XTAL2
OSC
÷ 16
PHASE
DETECTOR
PLL
VCO
÷2
÷M
SSC_CTL0
SSC_CTL1
SSC
Control
Logic
PIN ASSIGNMENT
FOUT
nFOUT
nc 1
nc 2
nc 3
nc 4
nc 5
nc 6
nc 7
nc 8
nc 9
SSC_CTL0 10
SSC_CTL1 11
VEE 12
TEST_I/O 13
VDD 14
28 nc
27 VDDI
26 XTAL2
25 XTAL1
24 nc
23 nc
22 VDDA
21 VEE
20 RESERVED
19 nc
18 VDDO
17 FOUT
16 nFOUT
15 VEE
TEST_I/O
ICS8431-01
28-Lead SOIC
M Package
Top View
ICS8431CM-01
www.icst.com/products/hiperclocks.html
1
REV. A JUNE 5, 2001
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