WEDPND16M72S-250BM 查看數據表（PDF） - White Electronic Designs => Micro Semi

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WEDPND16M72S-250BM

16Mx72 DDR SDRAM

White Electronic Designs => Micro Semi 

White Electronic Designs WEDPND16M72S-XBX

16Mx72 DDR SDRAM Preliminary*

FEATURES

n High Frequency = 200, 250, 266MHz

n Package:

• 219 Plastic Ball Grid Array (PBGA), 32 x 25mm

n 2.5V ±0.2V core power supply

n 2.5V I/O (SSTL_2 compatible)

n Differential clock inputs (CLK and CLK)

n Commands entered on each positive CLK edge

n Internal pipelined double-data-rate (DDR) architecture;

two data accesses per clock cycle

n Programmable Burst length: 2,4 or 8

n Bidirectional data strobe (DQS) transmitted/received

with data, i.e., source-synchronous data capture (one

per byte)

n DQS edge-aligned with data for READs; center-aligned

with data for WRITEs

n DLL to align DQ and DQS transitions with CLK

n Four internal banks for concurrent operation

n Two data mask (DM) pins for masking write data

n Programmable IOL/IOH option

n Auto precharge option

n Auto Refresh and Self Refresh Modes

n Commercial, Industrial and Military Temperature Ranges

n Organized as 16M x 72

n Weight: WEDPND16M72S-XBX - 2.5 grams typical

BENEFITS

n 40% SPACE SAVINGS

n Reduced part count

n Reduced I/O count

• 34% I/O Reduction

n Reduced trace lengths for lower parasitic capacitance

n Suitable for hi-reliability applications

n Laminate interposer for optimum TCE match

n Upgradeable to 32M x 72 density (contact factory for

information)

* This data sheet describes a product that is not fully qualified or characterized

and is subject to change without notice.

GENERAL DESCRIPTION

The 128MByte (1Gb) DDR SDRAM is a high-speed CMOS,

dynamic random-access, memory using 5 chips containing

268,435,456 bits. Each chip is internally configured as a

quad-bank DRAM. Each of the chip’s 67,108,864-bit banks

is organized as 8,192 rows by 512 columns by 16 bits.

The 128 MB DDR SDRAM uses a double data rate architec-

ture to achieve high-speed operation. The double data rate

architecture is essentially a 2n-prefetch architecture with an

interface designed to transfer two data words per clock

cycle at the I/O pins. A single read or write access for the

128MB DDR SDRAM effectively consists of a single 2n-bit

wide, one-clock-cycle data tansfer at the internal DRAM core

and two corresponding n-bit wide, one-half-clock-cycle

data transfers at the I/O pins.

A bidirectional data strobe (DQS) is transmitted externally, along

with data, for use in data capture at the receiver. DQS is a

December 2002 Rev. 3

Monolithic Solution

11.9

11.9

11.9

11.9

11.9

66

22.3 TSOP

66

TSOP

66

TSOP

66

66

TSOP TSOP

Area

I/O

Count

5 x 265mm2 = 1328mm2

5 x 66 pins = 330 pins

Actual Size

S

WEDPND16M72S-XBX A

V

I

White Electronic Designs 25

WEDPND16M72S-XBX

N

G

32

S

800mm2

40%

219 Balls

34%

1

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

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