74ACT843 查看數據表（PDF） - Fairchild Semiconductor
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74ACT843 Datasheet PDF : 6 Pages
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Functional Description
The ACT843 consists of nine D-type latches with 3-STATE
outputs. The flip-flops appear transparent to the data when
Latch Enable (LE) is HIGH. This allows asynchronous
operation, as the output transition follows the data in transi-
tion. On the LE HIGH-to-LOW transition, the data that
meets the setup times is latched. Data appears on the bus
when the Output Enable (OE) is LOW. When OE is HIGH,
the bus output is in the high impedance state. In addition to
Function Tables
the LE and OE pins, the ACT843 has a Clear (CLR) pin
and a Preset (PRE) pin. These pins are ideal for parity bus
interfacing in high performance systems. When CLR is
LOW, the outputs are LOW if OE is LOW. When CLR is
HIGH, data can be entered into the latch. When PRE is
LOW, the outputs are HIGH if OE is LOW. Preset overrides
CLR.
Inputs
CLR PRE OE LE
D
H
H
H
H
L
H
H
H
H
H
H
H
H
L
X
H
H
L
H
L
H
H
L
H
H
H
H
L
L
X
H
L
L
X
X
L
H
L
X
X
L
L
L
X
X
L
H
H
L
X
H
L
H
L
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
NC = No Change
Internal
Q
L
H
NC
L
H
NC
H
L
H
L
H
Outputs
O
Z
Z
Z
L
H
NC
H
L
H
Z
Z
Function
High Z
High Z
Latched
Transparent
Transparent
Latched
Preset
Clear
Preset
Clear/High Z
Preset/High Z
Logic Diagram
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