74ALS174N 查看數據表（PDF） - Philips Electronics
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74ALS174N Datasheet PDF : 8 Pages
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Philips Semiconductors
Hex D flip-flop
Product specification
74ALS174
FEATURES
• Four edge-triggered D flip-flops
• Buffered common clock
• Buffered asynchronous master reset
DESCRIPTION
The 74ALS174 has six edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered clock (CP)
and master reset (MR) inputs load and reset (clear) all flip-flops
simultaneously.
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
All Q outputs will be forced Low independent of clock or data inputs
by a Low voltage level on the MR input. The device is useful for
applications where true outputs only are required, and the clock and
master reset are common to all storage elements.
TYPE
74ALS174
TYPICAL
fMAX
70MHz
TYPICAL
SUPPLY CURRENT
(TOTAL)
7mA
PIN CONFIGURATION
MR 1
Q0 2
D0 3
D1 4
Q1 5
D2 6
Q2 7
GND 8
16 VCC
15 Q5
14 D5
13 D4
12 Q4
11 D3
10 Q3
9 CP
SF00188
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
16-pin plastic DIP
74ALS174N
16-pin plastic SO
74ALS174D
DRAWING
NUMBER
SOT38-4
SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74ALS (U.L.)
HIGH/LOW
D0 – D3
Data inputs
1.0/1.0
CP
Clock Pulse input (active rising edge)
1.0/1.0
MR
Master Reset input (active-Low)
1.0/1.0
Q0 – Q5
Data outputs
20/80
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
LOGIC SYMBOL
IEC/IEEE SYMBOL
3 4 6 11 13 14
D0 D1 D2 D3 D4 D5
9
CP
1
MR
Q0 Q1 Q2 Q3 Q4 Q5
VCC = Pin 16
GND = Pin 8
2 5 7 10 12 15
SF00189
9
C1
1
R
3
1D
4
6
11
13
14
LOAD VALUE
HIGH/LOW
20µA/0.1mA
20µA/0.1mA
20µA/0.1mA
0.4mA/8mA
2
5
7
10
12
15
SF00190
1991 Feb 08
2
853–1023 01670
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