74ALS175D 查看數據表（PDF） - Philips Electronics
零件编号
产品描述 (功能)
生产厂家
74ALS175D Datasheet PDF : 8 Pages
| |||
Philips Semiconductors
Quad D flip-flop
Product specification
74ALS175
FEATURES
• Four edge-triggered D flip-flops
• Buffered common clock
• Buffered asynchronous master reset
• True and complementary outputs
DESCRIPTION
The 74ALS175 is a quad, edge-triggered D-type flip-flops with
individual D inputs and both Q and Q outputs. The common buffered
clock (CP) and master reset (MR) inputs load and reset (clear) all
flip-flops simultaneously.
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
All Q outputs will be forced Low independent of clock or data inputs
by a Low voltage level on the MR input. The device is useful for
applications where both true and complement outputs are required,
and the clock and master reset are common to all storage elements.
TYPE
74ALS175
TYPICAL
fMAX
70MHz
TYPICAL
SUPPLY CURRENT
(TOTAL)
7mA
PIN CONFIGURATION
MR 1
Q0 2
Q0 3
D0 4
D1 5
Q1 6
Q1 7
GND 8
16 VCC
15 Q3
14 Q3
13 D3
12 D2
11 Q2
10 Q2
9 CP
SF00718
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
16-pin plastic DIP
74ALS175N
16-pin plastic SO
74ALS175D
DRAWING
NUMBER
SOT38-4
SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74ALS (U.L.)
HIGH/LOW
D0 – D3
Data inputs
1.0/1.0
CP
Clock Pulse input (active rising edge)
1.0/1.0
MR
Master Reset input (active-Low)
1.0/1.0
Q0 – Q3
True outputs
20/80
Q0 – Q3
Complementary outputs
20/80
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
LOGIC SYMBOL
IEC/IEEE SYMBOL
4 5 12 13
D0 D1 D2 D3
9
CP
1
MR
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3
1
R
9
C1
4
1D
5
12
2 3 7 6 10 11 15 14
13
VCC = Pin 16
GND = Pin 8
SF00719
LOAD VALUE
HIGH/LOW
20µA/0.1mA
20µA/0.1mA
20µA/0.1mA
0.4mA/8mA
0.4mA/8mA
2
3
7
6
10
11
15
14
SF00720
1991 Feb 08
2
853–1024 01670
Share Link: 