74ALS175D 查看數據表（PDF） - Philips Electronics
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74ALS175D Datasheet PDF : 8 Pages
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Philips Semiconductors
Quad D flip-flop
Product specification
74ALS175
AC WAVEFORMS
For all waveforms, VM = 1.3V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
CP VM
Qn
1/fmax
tw(H)
tPHL
VM
tw(L)
VM
VM
tPLH
VM
MR
VM
VM
tw(L)
tREC
CP
VM
tPHL
tPLH
tPHL
Qn
VM
Qn
VM
VM
tPLH
SF00722
Waveform 1. Propagation Delay for Clock Input to Output,
Clock Pulse Width,
and Maximum Clock Frequency
Qn
VM
Waveform 2. Master Reset Pulse Width,
Master Reset to Output Delay,
and Master Reset to Clock Recovery Time
SF00723
Dn
VM
VM
tsu(H) th(H)
VM
VM
tsu(L) th(L)
CP
VM
VM
SC00064
Waveform 3. Data Setup and Hold Times
TEST CIRCUIT AND WAVEFORMS
VIN
PULSE
GENERATOR
VCC
VOUT
D.U.T.
90%
NEGATIVE
PULSE
tw
VM
10%
tTHL (tff)
VM
10%
tTLH (tr )
90%
AMP (V)
0.3V
RT
CL RL
Test Circuit for Totem-pole Outputs
POSITIVE
PULSE
10%
tTLH (tr )
90%
VM
tw
tTHL (tf )
90%
VM
AMP (V)
10%
0.3V
DEFINITIONS:
RL = Load resistor;
see AC electrical characteristics for value.
CL = Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
RT = Termination resistance should be equal to ZOUT of
pulse generators.
Input Pulse Definition
INPUT PULSE REQUIREMENTS
Family
Amplitude VM Rep.Rate tw tTLH
74ALS 3.5V 1.3V 1MHz 500ns 2.0ns
tTHL
2.0ns
SC00005
1991 Feb 08
5
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