74ALVCH16843DGG 查看數據表（PDF） - Philips Electronics

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74ALVCH16843DGG

18-bit bus-interface D-type latch (3-State)

Philips Electronics 

Philips Semiconductors

18-bit bus interface D-type latch (3-State)

Product specification

74ALVCH16843

FEATURES

• Wide supply voltage range of 1.2V to 3.6V

• Complies with JEDEC standard no. 8-1A.

• CMOS low power consumption

• Direct interface with TTL levels

• Current drive ± 24 mA at 3.0 V

• MULTIBYTETM flow-through standard pin-out architecture

• Low inductance multiple VCC and GND pins for minimum noise

and ground bounce

• All data inputs have bus hold

• Output drive capability 50Ω transmission lines @ 85°C

DESCRIPTION

The 74ALVCH16843 has two 9–bit D-type latch featuring separate

D-type inputs for each latch and 3-State outputs for bus oriented

applications. The two sections of each register are controlled

independently by the latch enable (nLE), clear (nCLR),

preset (nPRE) and output enable (nOE) control gates.

When nOE is LOW, the data in the registers appear at the outputs.

When nOE is HIGH, the outputs are in the high impedance OFF

state. Operation of the nOE input does not affect the state of the

flip-flops.

The 74ALVCH16843 has active bus hold circuitry which is provided

to hold unused or floating data inputs at a valid logic level. This

feature eliminates the need for external pull-up or pull-down

resistors.

PIN CONFIGURATION

1CLR 1

1OE 2

1Q0 3

GND 4

1Q1 5

1Q2 6

VCC 7

1Q3 8

1Q4 9

1Q5 10

GND 11

1Q6 12

1Q7 13

1Q8 14

2Q0 15

2Q1 16

2Q2 17

GND 18

2Q3 19

2Q4 20

2Q5 21

VCC 22

2Q6 23

2Q7 24

GND 25

2Q8 26

2OE 27

2CLR 28

56 1LE

55 1PRE

54 1D0

53 GND

52 1D1

51 1D2

50 VCC

49 1D3

48 1D4

47 1D5

46 GND

45 1D6

44 1D7

43 1D8

42 2D0

41 2D1

40 2D2

39 GND

38 2D3

37 2D4

36 2D5

35 VCC

34 2D6

33 2D7

32 GND

31 2D8

30 2PRE

29

2LE

QUICK REFERENCE DATA

GND = 0V; Tamb = 25°C; tr = tf ≤ 2.5ns

SYMBOL

PARAMETER

CONDITIONS

SH00143

TYPICAL

tPHL/tPLH

CI

Propagation delay

nDn to nQn

Propagation delay

nLE to nQn

Input capacitance

VCC = 2.5V, CL = 30pF

VCC = 3.3V, CL = 50pF

VCC = 2.5V, CL = 30pF

VCC = 3.3V, CL = 50pF

CPD

Power dissipation capacitance per buffer

VI = GND to VCC1

2.2

2.1

2.3

2.0

5.0

transparent mode

Output enabled

17

Output disabled

3

Clocked mode

Output enabled

19

Output disabled

9

NOTES:

1. CPD is used to determine the dynamic power dissipation (PD in µW):

PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;

fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs.

UNIT

ns

ns

pF

pF

ORDERING INFORMATION

PACKAGES

56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II

TEMPERATURE

RANGE

–40°C to +85°C

OUTSIDE NORTH

AMERICA

74ALVCH16843 DGG

NORTH AMERICA

ACH16843 DGG

DRAWING

NUMBER

SOT364-1

1998 Aug 04

2

853–2108 019833

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