I74F112N 查看數據表（PDF） - Philips Electronics
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I74F112N Datasheet PDF : 10 Pages
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Philips Semiconductors
Dual J-K negative edge-triggered flip-flop
Product specification
74F112
FEATURE
• Industrial temperature range available (–40°C to +85°C)
DESCRIPTION
The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop,
feature individual J, K, Clock (CPn), Set (SD) and Reset (RD)
inputs, true (Qn) and complementary (Qn) outputs.
The SD and RD inputs, when Low, set or reset the outputs as shown
in the Function Table, regardless of the level at the other inputs.
A High level on the clock (CPn) input enables the J and K inputs and
data will be accepted. The logic levels at the J and K inputs may be
allowed to change while the CPn is High and flip-flop will perform
according to the Function Table as long as minimum setup and hold
times are observed. Output changes are initiated by the High-to-Low
transition of the CPn.
PIN CONFIGURATION
CP0 1
K0 2
J0 3
SD0 4
Q0 5
Q0 6
Q1 7
GND 8
16 VCC
15 RD0
14 RD1
13 CP1
12 K1
11 J1
10 SD1
9 Q1
SF00103
TYPE
74F112
TYPICAL PROPAGATION DELAY
100MHz
TYPICAL SUPPLY CURRENT (TOTAL)
15mA
ORDERING INFORMATION
DESCRIPTION
16-pin plastic DIP
ORDER CODE
COMMERCIAL RANGE
VCC = 5V ±10%, Tamb = 0°C to +70°C
N74F112N
INDUSTRIAL RANGE
VCC = 5V ±10%, Tamb = –40°C to +85°C
I74F112N
16-pin plastic SO
N74F112D
I74F112D
PKG DWG #
SOT38-4
SOT109-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74F (U.L.) HIGH/LOW
J0, J1
J inputs
1.0/1.0
K0, K1
K inputs
1.0/1.0
SD0, SD1
Set inputs (active Low)
1.0/5.0
RD0, RD1
Reset inputs (active Low)
1.0/5.0
CP0, CP1
Clock Pulse input (active falling edge)
1.0/4.0
Q0, Q0; Q1, Q1
Data outputs
50/33
NOTE:
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
LOAD VALUE HIGH/LOW
20µA/0.6mA
20µA/0.6mA
20µA/3.0mA
20µA/3.0mA
20µA/2.4mA
1.0mA/20mA
February 9, 1990
2
853–0338 98775
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