74F113 查看數據表（PDF） - Philips Electronics
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74F113 Datasheet PDF : 10 Pages
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Philips Semiconductors
Dual J-K negative edge-triggered flip-flops
without reset
Product specification
74F113
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST CONDITIONS1
LIMITS
UNIT
MIN TYP2 MAX
VOH
High-level output voltage
VCC = MIN, VIL = MAX,
VIH = MIN
IOH = MAX
±10%VCC
±5%VCC
2.5
2.7
3.4
V
V
VOL
Low-level output voltage
VCC = MIN, VIL = MAX,
VIH = MIN
IOL = MAX
±10%VCC
±5%VCC
0.30 0.50 V
0.30 0.50 V
VIK
Input clamp voltage
VCC = MIN, II = IIK
–0.73 –1.2 V
II
Input current at maximum input voltage VCC = MAX, VI = 7.0V
100 µA
IIH
High-level input current
VCC = MAX, VI = 2.7V
20
µA
Jn, Kn
–0.6 mA
IIL
Low-level input current
CPn
VCC = MAX, VI = 0.5V
–2.4 mA
SDn
–3.0 mA
IOS
Short-circuit output current3
VCC = MAX
-60
–150 mA
ICC
Supply current4 (total)
VCC = MAX
15
21
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at VCC = 5V, Tamb = 25°C.
3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, IOS tests should be performed last.
4. Measure ICC with the clock input grounded and all outputs open, then with Q and Q outputs high in turn.
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST
CONDITION
fmax
Maximum clock frequency Waveform 1
tPLH
Propagation delay
tPHL
CPn to Qn or Qn
Waveform 1
tPLH
Propagation delay
tPHL
SDn, to Qn or Qn
Waveform 2
VCC = +5.0V
Tamb = +25°C
CL = 50pF
RL = 500Ω
MIN TYP MAX
85 100
2.0 4.0 6.0
2.0 4.0 6.0
2.0 4.5 6.5
2.0 4.5 6.5
LIMITS
VCC = +5.0V ± 10%
Tamb = 0°C to +70°C
CL = 50pF
RL = 500Ω
MIN
MAX
80
2.0
7.0
2.0
7.0
2.0
7.5
2.0
7.5
VCC = +5.0V ± 10%
Tamb = –40°C to +85°C
CL = 50pF
RL = 500Ω
MIN
MAX
80
2.0
7.5
2.0
7.0
2.0
8.0
2.0
7.5
UNIT
ns
ns
ns
AC SETUP REQUIREMENTS
SYMBOL
PARAMETER
tsu (H)
tsu(L)
th (H)
th (L)
tw (H)
tw (L)
tw (L)
trec
Setup time, high or low
Jn, Kn to CPn
Hold time, high or low
Jn, Kn to CPn
CP pulse width,
high or low
SDn pulse width, low
Recovery time
SDn to CPn
TEST
CONDITION
Waveform 1
Waveform 1
Waveform 1
Waveform 2
Waveform 2
VCC = +5.0V
Tamb = +25°C
CL = 50pF
RL = 500Ω
MIN TYP MAX
4.0
3.5
0.0
0.0
4.5
4.5
4.5
LIMITS
VCC = +5.0V ± 10%
Tamb = 0°C to +70°C
CL = 50pF
RL = 500Ω
MIN
MAX
5.0
4.0
0.0
0.0
5.0
5.0
5.0
VCC = +5.0V ± 10%
Tamb = –40°C to +85°C
CL = 50pF
RL = 500Ω
MIN
MAX
5.0
4.5
0.0
0.0
5.0
5.0
5.0
UNIT
ns
ns
ns
ns
4.5
5.0
5.0
ns
1996 Mar 14
4
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