74F113SJX 查看數據表（PDF） - Fairchild Semiconductor
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74F113SJX Datasheet PDF : 6 Pages
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Unit Loading/Fan Out
Pin Names
Description
J1, J2, K1, K2
CP1, CP2
SD1, SD2
Q1, Q2, Q1, Q2
Data Inputs
Clock Pulse Inputs (Active Falling Edge)
Direct Set Inputs (Active LOW)
Outputs
Truth Table
U.L.
HIGH/LOW
1.0/1.0
1.0/4.0
1.0/5.0
50/33.3
Input IIH/IIL
Output IOH/IOL
20 µA/−0.6 mA
20 µA/−2.4 mA
20 µA/−3.0 mA
−1 mA/20 mA
Inputs
Outputs
SD
CP
J
K
Q
Q
L
H
H
X
X
h
l
X
h
h
H
Q0
L
L
Q0
H
H
h
l
H
L
H
l
l
Q0
Q0
H (h) = HIGH Voltage Level
L (l) = LOW Voltage level
] = HIGH-to-LOW Clock Transition
X = Immaterial
Q0 (Q0) = Before HIGH-to-LOW Transition of Clock
Lower case letters indicate the state of the referenced input or output prior to the HIGH-to-LOW clock transition.
Logic Diagram
(One Half Shown)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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