74F153PC 查看數據表（PDF） - Fairchild Semiconductor
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74F153PC Datasheet PDF : 6 Pages
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Unit Loading/Fan Out
Pin Names
Description
I0a–I3a
I0b–I3b
S0, S1
Ea
Eb
Za
Zb
Side A Data Inputs
Side B Data Inputs
Common Select Inputs
Side A Enable Input (Active LOW)
Side B Enable Input (Active LOW)
Side A Output
Side B Output
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
50/33.3
Input IIH/IIL
Output IOH/IOL
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
−1 mA/20 mA
−1 mA/20 mA
Truth Table
Select Inputs
Inputs (a or b)
Output
S0
S1 E I0 I1 I2 I3
Z
X
X HXXXX
L
L
L
L LXXX
L
L
L LHXXX H
H
L
LXLXX
L
H
L LXHXX H
L
H LXXLX
L
L
H LXXHX H
H
H LXXXL
L
H
H LXXXH H
H = HIGH Voltage Level
L = LOW
X = Immaterial
Functional Description
The F153 is a dual 4-input multiplexer. It can select two bits
of data from up to four sources under the control of the
common Select inputs (S0, S1). The two 4-input multiplexer
circuits have individual active LOW Enables (Ea, Eb) which
can be used to strobe the outputs independently. When the
Enables (Ea, Eb) are HIGH, the corresponding outputs (Za,
Zb) are forced LOW. The F153 is the logic implementation
of a 2-pole, 4-position switch, where the position of the
switch is determined by the logic levels supplied to the two
Select inputs. The logic equations for the outputs are as
follows:
Za = Ea•(I0a•S1•S0 + I1a•S1•S0 +
I2a•S1•S0 + I3a•S1•S0)
Zb = Eb•(I0b•S1•S0 + I1b•S1•S0 +
I2b•S1•S0 + I3b•S1•S0)
The F153 can be used to move data from a group of regis-
ters to a common output bus. The particular register from
which the data came would be determined by the state of
the Select inputs. A less obvious application is as a func-
tion generator. The F153 can generate two functions of
three variables. This is useful for implementing highly irreg-
ular random logic.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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