74F539CW 查看數據表（PDF） - Fairchild Semiconductor

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74F539CW

Dual 1-of-4 Decoder with 3-STATE Outputs

Fairchild Semiconductor 

April 1988

Revised August 1999

74F539

Dual 1-of-4 Decoder with 3-STATE Outputs

General Description

The 74F539 contains two independent decoders. Each

accepts two Address (A0, A1) input signals and decodes

them to select one of four mutually exclusive outputs. A

polarity control input (P) determines whether the outputs

are active HIGH (P = L) or active LOW (P = H). An active

LOW input Enable (E) is available for data demultiplexing;

data is routed to the selected output in non-inverted form in

the active LOW mode or in inverted form in the active HIGH

mode. A HIGH signal on the active LOW Output Enable

(OE) input forces the 3-STATE outputs to the high imped-

ance state.

Ordering Code:

Order Number Package Number

Package Description

74F539SC

M20B

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide

74F539PC

N20A

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

© 1999 Fairchild Semiconductor Corporation DS009552

www.fairchildsemi.com

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