74LV109N 查看數據表（PDF） - Philips Electronics
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74LV109N Datasheet PDF : 12 Pages
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Philips Semiconductors
Dual JK flip-flop with set and reset; positive-edge trigger
Product specification
74LV109
AC CHARACTERISTICS (Continued)
GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ
SYMBOL
PARAMETER
WAVEFORM
CONDITION
VCC(V)
1.2
tPHL
Propagation delay
nSD to nQ
Figure 2
2.0
2.7
3.0 to 3.6
1.2
tPHL
Propagation delay
nRD to nQ
Figure 2
2.0
2.7
3.0 to 3.6
1.2
tPLH
Propagation delay
nRD to nQ
Figure 2
2.0
2.7
3.0 to 3.6
tW
Clock pulse width
HIGH or LOW
Figure 1
2.0
2.7
3.0 to 3.6
tW
Set or reset pulse
width HIGH or LOW
Figure 2
2.0
2.7
3.0 to 3.6
1.2
trem
Removal time
nSD, nRD to nCP
Figure 2
2.0
2.7
3.0 to 3.6
1.2
tsu
Set-up time
nJ, nK to CP
Figure 1
2.0
2.7
3.0 to 3.6
1.2
th
Hold time
nJ, nK to nCP
Figure 1
2.0
2.7
3.0 to 3.6
fmax
Maximum clock
pulse frequency
Figure 1
2.0
2.7
3.0 to 3.6
NOTES:
1. Unless otherwise stated, all typical values are measured at Tamb = 25°C
2. Typical values are measured at VCC = 3.3 V.
LIMITS
–40 to +85 °C
MIN TYP1 MAX
75
26
46
19
36
172
29
75
26
46
19
36
152
29
70
24
44
18
33
132
26
34
12
25
9
20
72
34
9
25
6
20
52
35
24
12
18
9
14
72
30
22
10
16
8
13
62
–5
5
–2
5
–1
5
02
14
40
19
58
24
702
–40 to +125 °C
MIN MAX
60
44
35
60
44
35
54
40
32
41
30
24
41
30
24
29
21
17
26
19
15
5
5
5
12
16
20
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
MHz
1998 Apr 20
6
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