74LVC169(2009) 查看數據表（PDF） - NXP Semiconductors.
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74LVC169 Datasheet PDF : 22 Pages
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NXP Semiconductors
74LVC169
Presettable synchronous 4-bit up/down binary counter
PE
D0
D1
D2
D3
CP
U/D
CEP and CET
Q0
Q1
Q2
Q3
TC
13 14
load
15
012
count up
22 1
inhibit
Fig 7.
The following sequence is illustrated:
- Load (preset) to thirteen.
- Count up to fourteen, fifteen (maximum), zero, one and two.
- Inhibit.
- Countdown to one, zero (minimum), fifteen, fourteen and thirteen.
Typical timing sequence
0 15 14 13
count down
001aaa648
74LVC169_5
Product data sheet
Rev. 05 — 8 June 2009
© NXP B.V. 2009. All rights reserved.
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