74LVC38A 查看數據表（PDF） - Philips Electronics
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74LVC38A Datasheet PDF : 14 Pages
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Philips Semiconductors
Quad 2-input NAND gate (open drain)
Product specification
74LVC38A
FEATURES
• 5 V tolerant inputs for interfacing with 5 V logic
• Wide supply voltage range from 1.2 to 3.6 V
• CMOS low power consumption
• Direct interface with TTL levels
• Open-drain outputs
• Inputs accept voltages up to 5.5 V
• Complies with JEDEC standard no. 8-1A
• Specified from −40 to +85 °C and −40 to +125 °C.
DESCRIPTION
The 74LVC38A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices. This
feature allows the use of these devices as translators in a
mixed 3.3 and 5 V environment.
The 74LVC38A provides the 2-input NAND function.
The outputs of the 74LVC38A devices are open drain and
can be connected to other open-drain outputs to
implement active-LOW wired-OR or active-HIGH
wired-AND functions.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.
SYMBOL
tPZL
tPLZ
CI
CPD
PARAMETER
propagation delay nA, nB to nY
propagation delay nA, nB to nY
input capacitance
power dissipation capacitance per gate
CONDITIONS
CL = 50 pF; VCC = 3.3 V
CL = 50 pF; VCC = 3.3 V
VCC = 3.3 V; notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
TYPICAL
1.7
2.3
4.0
5.5
UNIT
ns
ns
pF
pF
ORDERING INFORMATION
TYPE NUMBER
74LVC38AD
74LVC38ADB
74LVC38APW
74LVC38ABQ
TEMPERATURE RANGE
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
−40 to +125 °C
PACKAGE
PINS
14
14
14
14
PACKAGE
SO14
SSOP14
TSSOP14
DHVQFN14
MATERIAL
plastic
plastic
plastic
plastic
CODE
SOT108-1
SOT337-1
SOT402-1
SOT762-1
2004 Mar 22
2
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