74LVQ161(2004) 查看數據表（PDF） - STMicroelectronics
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74LVQ161 Datasheet PDF : 14 Pages
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74LVQ161
Figure 2: Input And Output Equivalent Circuit
Table 2: Pin Description
Table 3: Truth Table
PIN N°
1
2
3, 4, 5, 6
7
10
9
14, 13, 12,
11
15
8
16
SYMBOL
CLEAR
CLOCK
A, B, C, D
PE
TE
LOAD
QA to QD
NAME AND FUNCTION
Asynchronous Master
Reset
Clock Input (LOW to
HIGH Edge Trigger)
Data Inputs
Count Enable Input
Count Enable Carry Input
Parallel Enable Input
Flip-Flop Outputs
CARRY OUT Terminal Count Output
GND Ground (0V)
VCC
Positive Supply Voltage
INPUTS
OUTPUTS
CLEAR LOAD
PE
TE
CK
L
X
X
X
X
L
L
L
H
L
X
X
A
B
C
H
H
X
L
H
H
L
X
NO CHANGE
NO CHANGE
H
H
H
H
H
X
X
X
COUNT UP
NO CHANGE
X : Don’t Care; A, B, C, D; Logic level of data input; CARRY OUT: TE x QA x QB x QC x QD
Figure 3: Logic Diagram
FUNCTION
L
RESET TO "0"
D
PRESET DATA
NO COUNT
NO COUNT
COUNT
NO COUNT
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