74LVX20TTR(2004) 查看數據表（PDF） - STMicroelectronics

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74LVX20TTR
(Rev.:2004)

LOW VOLTAGE CMOS DUAL 4-INPUT NAND GATE WITH 5V TOLERANT INPUTS

STMicroelectronics 

74LVX20

LOW VOLTAGE CMOS DUAL 4-INPUT NAND GATE

WITH 5V TOLERANT INPUTS

s HIGH SPEED:

tPD = 4.1ns (TYP.) at VCC = 3.3V

s 5V TOLERANT INPUTS

s INPUT VOLTAGE LEVEL:

VIL=0.8V, VIH=2V at VCC=3V

s LOW POWER DISSIPATION:

ICC = 2 µA (MAX.) at TA=25°C

s LOW NOISE:

VOLP = 0.3V (TYP.) at VCC = 3.3V

s SYMMETRICAL OUTPUT IMPEDANCE:

|IOH| = IOL = 4mA (MIN)

s BALANCED PROPAGATION DELAYS:

tPLH ≅ tPHL

s OPERATING VOLTAGE RANGE:

VCC(OPR) = 2V to 3.6V (1.2V Data Retention)

s PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 20

s IMPROVED LATCH-UP IMMUNITY

s POWER DOWN PROTECTION ON INPUTS

DESCRIPTION

The 74LVX20 is a low voltage CMOS DUAL

4-INPUT NAND GATE fabricated with sub-micron

silicon gate and double-layer metal wiring C2MOS

technology. It is ideal for low power, battery

operated and low noise 3.3V applications.

SOP

TSSOP

Table 1: Order Codes

PACKAGE

SOP

TSSOP

T&R

74LVX20MTR

74LVX20TTR

The internal circuit is composed of 3 stages

including buffer output, which provides high noise

immunity and stable output.

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage.

This device can be used to interface 5V to 3V

system. It combines high speed performance with

the true CMOS low power consumption.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

Figure 1: Pin Connection And IEC Logic Symbols

August 2004

Rev. 3

1/11

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