SY100S834LZCTR 查看數據表（PDF） - Micrel
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SY100S834LZCTR Datasheet PDF : 5 Pages
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Micrel, Inc.
TIMING DIAGRAM
CLK
FSEL = 0
Q0
Q1
Q2
FSEL = 1
Q0
Q1
Q2
EN
Internal Clock
Disabled
Precision Edge®
SY100S834
SY100S834L
The EN signal will freeze the internal clocks to the flip-flops on the first falling edge of CLK after its assertion. The internal dividers will maintain
their state during the internal clock freeze and will return to clocking once the internal clocks are unfrozen. The outputs will transition to their
next states in the same manner, time and relationship as they would have had the EN signal not been asserted.
M9999-032206
hbwhelp@micrel.com or (408) 955-1690
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