7546 查看數據表（PDF） - Renesas Electronics

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7546

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Renesas Electronics 

7546 Group

Processor status register (PS)

The processor status register is an 8-bit register consisting of

flags which indicate the status of the processor after an arithmetic

operation. Branch operations can be performed by testing the

Carry (C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N)

flag. In decimal mode, the Z, V, N flags are not valid.

After reset, the Interrupt disable (I) flag is set to “1”, but all other

flags are undefined. Since the Index X mode (T) and Decimal

mode (D) flags directly affect arithmetic operations, they should

be initialized in the beginning of a program.

(1) Carry flag (C)

The C flag contains a carry or borrow generated by the arithmetic

logic unit (ALU) immediately after an arithmetic operation. It can

also be changed by a shift or rotate instruction.

(2) Zero flag (Z)

The Z flag is set if the result of an immediate arithmetic operation

or a data transfer is “0”, and cleared if the result is anything other

than “0”.

(5) Break flag (B)

The B flag is used to indicate that the current interrupt was gener-

ated by the BRK instruction. The BRK flag in the processor status

register is always “0”. When the BRK instruction is used to gener-

ate an interrupt, the processor status register is pushed onto the

stack with the break flag set to “1”. The saved processor status is

the only place where the break flag is ever set.

(6) Index X mode flag (T)

When the T flag is “0”, arithmetic operations are performed be-

tween accumulator and memory, e.g. the results of an operation

between two memory locations is stored in the accumulator. When

the T flag is “1”, direct arithmetic operations and direct data trans-

fers are enabled between memory locations, i.e. between memory

and memory, memory and I/O, and I/O and I/O. In this case, the

result of an arithmetic operation performed on data in memory lo-

cation 1 and memory location 2 is stored in memory location 1.

The address of memory location 1 is specified by index register X,

and the address of memory location 2 is specified by normal ad-

dressing modes.

(3) Interrupt disable flag (I)

The I flag disables all interrupts except for the interrupt generated

by the BRK instruction. Interrupts are disabled when the I flag is

“1”.

When an interrupt occurs, this flag is automatically set to “1” to

prevent other interrupts from interfering until the current interrupt

is serviced.

(4) Decimal mode flag (D)

The D flag determines whether additions and subtractions are ex-

ecuted in binary or decimal. Binary arithmetic is executed when

this flag is “0”; decimal arithmetic is executed when it is “1”.

Decimal correction is automatic in decimal mode. Only the ADC

and SBC instructions can be used for decimal arithmetic.

(7) Overflow flag (V)

The V flag is used during the addition or subtraction of one byte

of signed data. It is set if the result exceeds +127 to -128. When

the BIT instruction is executed, bit 6 of the memory location oper-

ated on by the BIT instruction is stored in the overflow flag.

(8) Negative flag (N)

The N flag is set if the result of an arithmetic operation or data

transfer is negative. When the BIT instruction is executed, bit 7 of

the memory location operated on by the BIT instruction is stored in

the negative flag.

Table 5 Set and clear instructions of each bit of processor status register

Set instruction

Clear instruction

C flag

SEC

CLC

Z flag

–

–

I flag

SEI

CLI

D flag

SED

CLD

B flag

–

–

T flag

SET

CLT

V flag

–

CLV

N flag

–

–

Rev.1.21 Nov 15, 2006 page 12 of 93

REJ03B0160-0121

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