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7546

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Renesas Electronics 

7546 Group

[CPU mode register] CPUM

The CPU mode register contains the stack page selection bit, etc..

This register is allocated at address 003B16.

Some function of the CPU mode register can be controlled by the

function set ROM data 2.

Switching method of CPU mode register

Switch the CPU mode register (CPUM) at the head of program af-

ter releasing Reset in the following method.

b7

b0

CPU mode register (Note 1)

(CPUM: address 003B16, initial value: 8016)

Processor mode bits

b1 b0

0 0 Single-chip mode

0 1 Not available

1 0 Not available

1 1 Not available

Stack page selection bit

0 : 0 page

1 : 1 page

On-chip oscillator oscillation control bit (Note 3)

0 : On-chip oscillator oscillation enabled

1 : On-chip oscillator oscillation stop

Control by Function set ROM data 2

(FSROM2: address FFDA16) (Note 2)

This cannot be controlled by FSROM2.

This cannot be controlled by FSROM2.

This bit function can be set by setting bit 4 of FSROM2. (Note 3)

Bit 4 of FSROM2 = 0: Bit 3 of CPUM is fixed to “0”.

Bit 4 of FSROM2 = 1: Bit 3 of CPUM is “0” or “1”.

XIN oscillation control bit

0 : Ceramic or RC oscillation enabled

1 : Ceramic or RC oscillation stop

This cannot be controlled by FSROM2.

Oscillation mode selection bit (Note 1, Note 4)

This bit function can be set by setting bit 5 of FSROM2. (Note 4)

0 : Ceramic oscillation

Bit 5 of FSROM2 = 0: Bit 5 of CPUM is fixed to “0”.

1 : RC oscillation

Bit 5 of FSROM2 = 1: Bit 5 of CPUM is “0” or “1”.

Clock division ratio selection bits

This cannot be controlled by FSROM2.

b7 b6

0 0 : f(φ) = f(XIN)/2 (High-speed mode)

0 1 : f(φ) = f(XIN)/8 (Middle-speed mode)

1 0 : applied from on-chip oscillator

1 1 : f(φ) = f(XIN)/1 (Double-speed mode)(Note 5)

Note 1: When the setting by the function set ROM data 2 (FSROM2) is performed, the initial value of CPUM is changed

after releasing reset since bit 5 of CPUM is fixed.

2: The setting values of FSROM2 become valid by setting “0” to bit 0 of function set ROM data 0 (FSROM0).

The setting values of FSROM2 are invalid by setting “1” to this bit.

(In order that FSROM2 is invalid, write to CPUM after releasing reset.)

3: When bit 4 of FSROM2 is set to “0”, the operation of on-chip oscillator cannot be stopped.

Since the on-chip oscillator is not stopped also in the stop mode, the dissipation current in the stop mode is increased.

4: The setting value of bit 5 of CPUM can be fixed after releasing reset by setting value of bit 5 of FSROM2.

Also, when the setting of FSROM2 is invalid, this bit can be rewritten only once after releasing reset.

After rewriting it is disable to write any data to this bit.

This bit is initialized by reset, and then, rewriting it is enabled.

5: This setting can be used only at ceramic oscillation. Do not use this at RC oscillation.

Fig. 11 Structure of CPU mode register

After releasing reset

Start with an on-chip oscillator

Switch the oscillation mode

selection bit (bit 5 of CPUM)

An initial value is set as a ceramic oscillation mode.

When it is switched to an RC oscillation, its oscillation starts.

Wait by on-chip oscillator operation

until establishment of oscillator clock

When using a ceramic oscillation, wait until establlishment of

oscillation from oscillation starts.

When using an RC oscillation, wait time is not required

basically (time to execute the instruction to switch from an

on-chip oscillator meets the requirement).

Switch the clock division ratio

Select 1/1, 1/2, 1/8 or on-chip oscillator.

selection bits (bits 6 and 7 of CPUM)

Main routine

Note: After system is released from reset, an on-chip oscillator turns active automatically and system operation

is started.

Fig. 12 Switching method of CPU mode register

Rev.1.21 Nov 15, 2006 page 14 of 93

REJ03B0160-0121

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