78P2342JAT-IGT 查看數據表（PDF） - Teridian Semiconductor Corporation
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78P2342JAT-IGT Datasheet PDF : 36 Pages
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78P2342JAT
2-port E3/DS3/STS-1 LIU
with Jitter Attenuator
REGISTER DESCRIPTION (continued)
LEGEND
TYPE DESCRIPTION
R/O Read only
TYPE DESCRIPTION
R/W Read or Write
GLOBAL REGISTERS
ADDRESS 0-0: MASTER CONTROL REGISTER
BIT
NAME
TYPE
DFLT
VALUE
DESCRIPTION
Register Control Enable:
7 REGEN R/W
0 : Pin selection overrides register settings
0
1 : Device is controlled via register set.
NOTE: Pin 15 (ENDECB) must be tied low when REGEN is enabled.
Line Speed Selection:
6
DS3
R/W
X
Selects the line speed of all channels as well as the input clock frequency
at the CKREF pin.
[DS3 E3] = 00 : STS-1 (51.840MHz)
01 : E3 (34.368MHz)
5
E3
R/W
X
10 : DS3 (44.736MHz)
11 : STS-1 (51.840MHz)
NOTE: The default values of these register bits depend on the state of
the MSL0 pin upon power-up or reset.
Encoder/Decoder Disable:
4 ENDECB R/W
0
0 : selects NRZ digital data interface
1 : selects AMI digital data interface
NOTE: Relevant only when the REGEN bit is set. Otherwise, ENDECB
pin selection prevails.
RCLK Polarity Selection:
3 RCLKP R/W
0
0 : Receive Data clocked out on the falling-edge of RCLK
1 : Receive Data clocked out on the rising-edge of RCLK
TCLK Polarity Selection:
2 TCLKP R/W
0
0 : Transmit Data clocked in on the rising-edge of TCLK
1 : Transmit Data clocked in on the falling-edge of TCLK
1 RSVD R/O
-- Reserved
0 SRST R/W
Register Soft-Reset:
0
When this bit is set, all registers are reset to their default values. Also
resets Jitter Attenuator to “centered” states. This register bit is self-
clearing.
Page 8 of 36
2005 Teridian Semiconductor Corporation
Rev 2.2
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