78P2351-IGTR 查看數據表（PDF） - Teridian Semiconductor Corporation

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78P2351-IGTR

Single Channel OC-3/ STM1-E/ E4 LIU

Teridian Semiconductor Corporation 

Transmit Driver

In CMI (electrical) mode, the CMIP/N pins are biased

and terminated off-chip. They interface to 75Ω

coaxial cable through a 1:1 wideband transformer

and coaxial RF connectors. Reference application

notes for schematic and layout guidelines.

The transmitter encodes the data using CMI line

coding and shapes an analog signal to meet the

appropriate ITU-T G.703 template. The CMI outputs

are tri-stated during transmit disable and transmit

power-down for redundancy applications.

Note: To avoid reflections causing unwanted

board noise, it’s recommended to power-down

unused transmit ports that are not terminated

with cable to an Rx input port.

When the CMI pin is low, the chip is in Fiber (NRZ

pass-through) mode and interfaces directly to an

optical transceiver module. The ECLP/N pins are

internally biased and output NRZ data at LVPECL

levels. The CMI driver, encoder and decoder are

disabled in Fiber (NRZ) mode.

Transmit Monitor Mode

An optional redundant transmit output is available in

CMI mode for transmit monitoring. These outputs

(CMI2P/N) are enabled when the RCSL pin or RCSL

register bit is activated.

CMI2P/N

CMI

Coax

XFMR

CMI

Coax

CMIP/N

XFMR

TDK

78P2351

RXP/N

CMI

Coax

XFMR

Figure 6: Transmit Monitor Output

Clock Synthesizer

The transmit clock synthesizer is a low-jitter DLL that

generates a 278.528/311.04 MHz clock for the CMI

encoder. It is also used in both the receive and

transmit sides for clock and data recovery.

Note: This 2x line rate clock is also available at

the TXCKxP/N pins for downstream

synchronization or system debug.

78P2351

Single Channel

OC-3/ STM1-E/ E4 LIU

Transmit Backplane Equalizer

An optional fixed LVPECL equalizer is integrated in

the transmit path for architectures that use LIUs on

active interface cards. The fixed equalizer can

compensate for up to 1.5m of trace and can be

enabled by the TXOUT1 pin or TXEQ bit as follows:

TXOUT1 pin

Low

Float

TXEQ bit

1

0

Tx Equalizer

Enabled

Disabled

Transmit Loss of Lock

In transmit modes using the integrated CDR, the

78P2351 will declare a loss of lock condition when

there is no valid signal detected at the SIDP/N data

inputs.

Note: The Tx LOL indicator is invalid and

undefined when the parallel (nibble) interface is

selected.

POWER-DOWN FUNCTION

Power-down control is provided to allow the

78P2351 to be shut off. Transmit and receive

power-down can be set independently through SW

control. Global power-down is achieved by

powering down both the transmitter and receiver.

Note: The serial interface and configuration

registers are not affected by power-down.

In HW mode, the transmitters can be powered down

using the TXPD control pin.

Page: 7 of 42

2006 Teridian Semiconductor Corporation

Rev. 2.4

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