78P2351R 查看數據表（PDF） - Teridian Semiconductor Corporation

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78P2351R

Serial 155M NRZ to CMI Converter

Teridian Semiconductor Corporation 

78P2351R

Serial 155M

NRZ to CMI Converter

REGISTER DESCRIPTION (continued)

PORT-SPECIFIC REGISTERS

For PA[3:0] = 1 only. Accessing a register with port address greater than 1 constitutes an invalid command, and

the read/write operation will be ignored.

ADDRESS 1-0: MODE CONTROL REGISTER

BIT

NAME

TYPE

DFLT

VALUE

DESCRIPTION

7 PDTX R/W

Transmitter Power-Down:

0

0 : Normal Operation

1 : Power-Down. CMI Transmit output is tri-stated.

6 PDRX R/W

Receiver Power-Down:

0

0 : Normal Operation

1 : Power-Down

5

--

R/W

0 Reserved.

4 SMOD[1] R/W

3 SMOD[0] R/W

2

MON

R/W

Serial Mode Interface Selection:

SMOD[1] SMOD[0]

0

X

0 Reserved

1

0 Synchronous data is passed through the CDR and

then through the FIFO.

0

1 Plesiochronous data is passed through the CDR to

recover a clock, but the FIFO is bypassed because

the data is not synchronous with the reference clock.

1

X

1 Loop Timing Mode Enable: The recovered receive

clock is used as the reference for the transmit DLL

and FIFO.

Note: Default values depend on the CKMODE pin setting upon reset or

power up.

Receive Monitor Mode Enable:

0

0: Normal Operation

1: Adds 20dB of flat gain to the receive signal before equalization.

1:0

--

R/W

01 Reserved.

Page: 10 of 31

2006 Teridian Semiconductor Corporation

Rev. 2.1

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