78P2351R-IM 查看數據表（PDF） - Teridian Semiconductor Corporation

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78P2351R-IM

Serial 155M NRZ to CMI Converter

Teridian Semiconductor Corporation 

TRANSMITTER OPERATION

The transmitter section generates an adjustable

ITU-T G.703 compliant analog signal for

transmission through a wideband transformer onto

75Ω coaxial cable. Differential NRZ data is input to

the 78P2351R on the SIDP/N pins at LVPECL levels

and passed to a low jitter clock and data recovery

circuit. An optional clock decoupling FIFO is

provided to decouple the on chip and off chip clocks.

The NRZ data is encoded using CMI line coding to

ensure an adequate number of transitions.

Each of the transmit timing modes can be configured

in HW mode or SW mode as shown in the table

below.

Tx Mode

HW Control

CKMODE

SW Control

SMOD[1:0]

Reserved

Low

00

Synchronous

(FIFO enabled)

Floating

10

Plesiochronous

High

01

Loop-timing

n/a

11

Plesiochronous Mode

Plesiochronous mode represents a common

condition where a synchronous reference clock is

not available. In this mode, the 78P2351R will

recover the transmit clock from the plesiochronous

data and bypass the internal FIFO and re-timing

block. This mode is commonly used for mezzanine

cards, modules, and any application where the

reference clock can’t always be synchronous to the

transmit source clock/data

System

Clock

XO

Framer/

Mapper

NRZ

NRZ

CKREFP

SIDP/N

SODP/N

TDK

78P2351R

CMI

Coax

CMIP/N

XFMR

CMI

Coax

RXP/N

XFMR

Figure 1: Plesiochronous Mode

78P2351R

Serial 155M

NRZ to CMI Converter

Synchronous Mode

When the NRZ transmit data is source synchronous

with the reference clock applied at CKREFP/N as

shown in Figure 2, the 78P2351R can be optionally

used in synchronous mode or re-timing mode. In

this mode, the 78P2351R will recover the clock from

the NRZ data input and re-time the data in an

integrated +/- 4-bit FIFO.

System Reference Clock

Framer/

Mapper

NRZ

NRZ

CKREFP/N

SIDP/N

SODP/N

TDK

78P2351R

CMI

Coax

CMIP/N

XFMR

CMI

Coax

RXP/N

XFMR

Figure 2: Synchronous

Since the reference clock and transmit clock/data go

through different delay paths, it is inevitable that the

phase relationship between the two clocks can vary

in a bounded manner due to the fact that the

absolute delays in the two paths can vary over time.

The transmit FIFO allows long-term clock phase drift

between the Tx clock and system reference clock,

not exceeding +/- 25.6ns, to be handled without

transmit error. If the clock wander exceeds the

specified limits, the FIFO will over or under flow, and

the FERR register signal will be asserted. This

signal can be used to trigger an interrupt. This

interrupt event is automatically cleared when a FIFO

Reset (FRST) pulse is applied, and the FIFO is re-

centered.

Notes:

1) External remote loopbacks (i.e. loopback

within framer) are not possible in

synchronous operation (FIFO enabled)

unless the data is re-justified to be

synchronous to the system reference clock

or the 78P2351R is configured for loop-

timing operation.

2) During IC power-up or transmit power-up,

the clocks going to the FIFO may not be

stable and cause the FIFO to overflow or

underflow. As such, the FIFO should be

manually reset using FRST anytime the

transmitter is powered-up.

Clock Synthesizer

The transmit clock synthesizer is a low-jitter PLL that

generates a 311.04 MHz clock for the CMI encoder.

A synthesized 155.52 MHz reference clock is also

used in both the receive and transmit sides for clock

and data recovery.

Page: 5 of 31

2006 Teridian Semiconductor Corporation

Rev. 2.1

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