78P2351R 查看數據表（PDF） - Teridian Semiconductor Corporation
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78P2351R Datasheet PDF : 31 Pages
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REGISTER DESCRIPTION (continued)
LEGEND
TYPE
R/O
R/C
DESCRIPTION
Read only
Read and Clear
TYPE DESCRIPTION
R/W Read or Write
78P2351R
Serial 155M
NRZ to CMI Converter
GLOBAL REGISTERS
ADDRESS 0-0: MASTER CONTROL REGISTER
BIT
NAME
TYPE
DFLT
VALUE
DESCRIPTION
7:5
--
R/W
0X0 Reserved.
CKSL
4:3
[1:0]
R/W
Reference Clock Frequency Select:
Selects the reference clock frequency input at CKREFP/N pins.
11: 155.52 MHz (differential LVPECL input)
X
10: 77.76 MHz (single-ended CMOS input) – Tie CKREFN to ground.
00: 19.44 MHz (single-ended CMOS input) – Tie CKREFN to ground.
Note: Default values depend on the CKSL pin setting upon reset or
power up.
2:1
--
R/W
X0 Reserved.
0 SRST R/W
Register Soft-Reset:
0
When this bit is set, all registers are reset to their default values. This
register bit is self-clearing.
ADDRESS 0-1: RESERVED
BIT NAME TYPE
DFLT
VALUE
7:0
--
R/W 00100X11
DESCRIPTION
Reserved.
ADDRESS 0-2: RESERVED
BIT NAME TYPE
DFLT
VALUE
7:0
--
R/W XXXXXXX0
DESCRIPTION
Reserved.
Page: 9 of 31
2006 Teridian Semiconductor Corporation
Rev. 2.1
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