7700 查看數據表（PDF） - Renesas Electronics
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7700 Datasheet PDF : 531 Pages
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Table of contents
4.2 Clocks ...................................................................................................................................... 4-4
4.2.1 Clocks generated in clock generating circuit ............................................................. 4-5
4.2.2 Clock control register 0 ................................................................................................. 4-6
4.2.3 Particular function select register 0 ............................................................................. 4-9
[Precautions for clock generating circuit] ........................................................................... 4-11
CHAPTER 5. INPUT/OUTPUT PINS
5.1 Overview .................................................................................................................................. 5-2
5.2 Programmable I/O ports ....................................................................................................... 5-2
5.2.1 Direction register ............................................................................................................ 5-3
5.2.2 Port register .................................................................................................................... 5-4
5.2.3 Pin P6OUTCUT/INT4 (Port-P6-output-cutoff signal input pin) ..................................... 5-6
5.3 Examples of handling unused pins .................................................................................. 5-7
CHAPTER 6. INTERRUPTS
6.1 Overview .................................................................................................................................. 6-2
6.2 Interrupt sources ................................................................................................................... 6-3
6.3 Interrupt control ..................................................................................................................... 6-5
6.3.1 Interrupt disable flag (I) ................................................................................................ 6-7
6.3.2 Interrupt request bit ....................................................................................................... 6-7
6.3.3 Interrupt priority level select bits and Processor interrupt priority level (IPL) ...... 6-7
6.4 Interrupt priority level .......................................................................................................... 6-9
6.5 Interrupt priority level detection circuit ......................................................................... 6-10
6.6 Interrupt priority level detection time ............................................................................ 6-12
6.7 Sequence from acceptance of interrupt request until execution of interrupt routine ... 6-13
6.7.1 Change in IPL at acceptance of interrupt request .................................................. 6-14
6.7.2 Push operation for registers ....................................................................................... 6-15
6.8 Return from interrupt routine ........................................................................................... 6-16
6.9 Multiple interrupts ............................................................................................................... 6-16
6.10 External interrupts ............................................................................................................ 6-18
6.10.1 INTi interrupt ............................................................................................................... 6-18
6.10.2 Functions of INTi interrupt request bit .................................................................... 6-21
6.10.3 Switching of INTi to interrupt request occurrence factor ...................................... 6-22
[Precautions for interrupts] ..................................................................................................... 6-23
CHAPTER 7. TIMER A
7.1 Overview .................................................................................................................................. 7-2
7.2 Block description .................................................................................................................. 7-4
7.2.1 Counter and Reload register (timer Ai register) ........................................................ 7-5
7.2.2 Timer A clock division select register ......................................................................... 7-6
7.2.3 Count start register ........................................................................................................ 7-7
7.2.4 Timer Ai mode register ................................................................................................. 7-8
7.2.5 Timer Ai interrupt control register ................................................................................ 7-9
7.2.6 Port P2 and port P6 direction registers .................................................................... 7-10
7.3 Timer mode ........................................................................................................................... 7-11
7.3.1 Setting for timer mode ................................................................................................ 7-13
7.3.2 Operation in timer mode ............................................................................................. 7-14
7.3.3 Select function .............................................................................................................. 7-15
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7906 Group User’s Manual Rev.2.0
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