7C256-10 查看數據表（PDF） - Alliance Semiconductor

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7C256-10

High Performance 32K×8 CMOS SRAM

Alliance Semiconductor 

AS7C256

AS7C256L

WRITE CYCLE 11

Parameter

Write Cycle Time

Chip Enable to Write End

Address Setup to Write End

Address Setup Time

Write Pulse Width

Address Hold From End of Write

Data Valid to Write End

Data Hold Time

Write Enable to Output in High Z

Output Active from Write End

(VCC = 5V±10%, GND = 0V, Ta = 0°C to +70°C)

-10

-12

-15

-20

-25

-35

Symbol Min Max Min Max Min Max Min Max Min Max Min Max Unit Notes

tWC

10 – 12 – 15 – 20 – 20 – 30 – ns

tCW

9 – 10 – 12 – 12 – 15 – 20 – ns

tAW

9 – 10 – 12 – 12 – 15 – 20 – ns

tAS

0 – 0 – 0 – 0 – 0 – 0 – ns

tWP

7 – 8 – 9 – 12 – 15 – 17 – ns

tAH

0 – 0 – 0 – 0 – 0 – 0 – ns

tDW

6 – 6 – 8 – 10 – 10 – 15 – ns

tDH

0 – 0 – 0 – 0 – 0 – 0 – ns 4, 5

tWZ

– 5 – 5 – 5 – 5 – 5 – 5 ns 4, 5

tOW

3 – 3 – 3 – 3 – 3 – 3 – ns 4, 5

TIMING WAVEFORM OF WRITE CYCLE 1 10, 11

(WE Controlled)

Address

WE

Din

Dout

tWC

tAW

tAH

tASAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA

tWZ

tWP

tDW

tDH

Data Valid

tOW

TIMING WAVEFORM OF WRITE CYCLE 2 10, 11

AS7C256-05

(CE Controlled)

tWC

tAW

Address

tAS

tCW

CE

WE AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA

tWP

tWZ

Din

Dout

AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA

tAH

AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA

tDW

tDH

Data Valid

AS7C256-06

5

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