White Electronic Designs
EDI88130CS
ADDRESS
DATA I/O
FIGURE 2 – TIMING WAVEFORM - READ CYCLES
tAVAV
ADDRESS 1
ADDRESS 2
tAVQV
tAVQX
DATA 1
DATA 2
READ CYCLE 1 (WE# HIGH; OE#, CS# LOW)
ADDRESS
CS1#
Icc
CS2
OE#
DATA I/O
tAVAV
tAVQV
tE1LQV
tE1LQX
tE1LICCH
tE2HQV
tE2HICCH
tE2HQX
tGLQV
tGLQX
tE1HQZ
tE1HICCL
tE2LICCL
tGHQZ
READ CYCLE 2 (CS1# AND/OR CS2 CONTROLLED, WE# HIGH)
FIGURE 3 – WRITE CYCLE 1
ADDRESS
WE#
CS1#
tAVWL
tAVAV
tAVWH
tWLWH
tE1LWH
tWHAX
CS2
DATA IN
DATA OUT
tE2HWH
tWLQZ
tDVWH
tWHDX
tWHQX
WRITE CYCLE 1 - LATE WRITE, WE# CONTROLLED
FIGURE 4 – WRITE CYCLES 2
ADDRESS
WE#
tAVE1L
tAVAV
tE1LE1H
tE1HAX
ADDRESS
WE#
WRITE CYCLES 3
tAVAV
tAVE2H
tE2HE2L
tE2LAX
CS1#
CS1#
CS2
DATA I/O
tDVE1H
tE1HDX
CS2
DATA I/O
tDVE2L
tE2LDX
WRITE CYCLE 2 - EARLY WRITE, CS1# CONTROLLED
WRITE CYCLE 3 - EARLY WRITE, CS2 CONTROLLED
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2002
Rev. 11
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com