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82443LX

INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC)

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INTEL 82443LX (PAC)

In Host-to-PCI transfers, depending on the PCI address space being accessed, the address will be either

translated or directly forwarded on the PCI bus. If the access is to a PCI configuration space, the processor

I/O cycle is mapped to a configuration cycle. If the access is to a PCI I/O or memory space, the processor

address is passed without modification to the PCI bus, unless it hits a certain PCI memory address range

(later referred in a document as the A.G.P. Aperture or Graphics Aperture) dedicated for graphics memory

address space. If this space, or a portion of it, is mapped to main memory, then the address will be translated

via the A.G.P. address remapping mechanism. The request will also be forwarded to the DRAM subsystem.

Host cycles forwarded to A.G.P. are defined by the A.G.P. address map.

PAC also receives requests from PCI bus and A.G.P. bus initiators for access to main memory. If a target

address is within the graphics aperture, then the request is translated into the appropriate memory address.

A.G.P. accesses destined to the graphics aperture are not snooped on the host bus because coherency of

aperture data is maintained by software. All accesses to the aperture, from the Host, PCI or A.G.P., are

translated using the A.G.P. address remapping mechanism.

DRAM Interface

The PAC integrates a main memory controller that supports a 64/72-bit DRAM interface. The DRAM

controller supports the following features:

• DRAM type. Extended Data Out (EDO) and Synchronous (SDRAM) DRAM controller optimized for dual-

bank SDRAM organization

• Memory Size.

 SDRAM: 8 MB to 512 MB with eight memory rows

 EDO: 8 MB to 1 GB with eight memory rows

• Addressing Type. Symmetrical and Asymmetrical addressing

• Memory Modules: Single and double density DIMMs

• Configurable DRAM Interface.

 Configuration #1: Large Memory Array

• Support for single-sided DIMMs based on x4 DRAMs

• Support for single and double-sided x8 and x16 DIMMs

• External buffering is required on MAA[13:2] signals (Do not buffer MAA[1:0] or MAB[1:0])

• 8 Row, 4 DS DIMM socket configuration

 Configuration #2: Small Memory Array

• Support for single and double-sided x8 and x16 DIMMs only

• Two copies of MA[13:2] signals supplied by the PAC (no external buffers required on MA signals)

• 6 Row, 3 DS DIMM socket configuration

• DRAM device technology. 4 Mbit, 16 Mbit and 64 Mbit

• DRAM Speeds. 50 ns and 60 ns for asynchronous EDO DRAM and equivalent SDRAM 66-MHz

parameters for synchronous memory.

The 440LX AGPset also provides a DIMM plug-and-play support via Serial Presence Detect (SPD)

mechanism. This is supported via the PIIX4 SMB interface. The PAC provides optional data integrity features

including EC or ECC in the memory array. Error Checking (EC) mode provides single and multiple bit error

detection. In ECC mode, the PAC provides error checking and correction of the data during reads from the

DRAM. The PAC supports multiple-bit error detection and single-bit error correction when ECC mode is

enabled and single/multi-bit error detection when correction is disabled. During writes to the DRAM, PAC

generates ECC for the data.

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