82443ZX 查看數據表（PDF） - Intel

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82443ZX

Intel® 440ZX AGPset: 82443ZX Host Bridge/Controller

Intel 

4

Functional Description ...............................................................................................4-1

4.1 System Address Map....................................................................................4-1

4.1.1 Memory Address Ranges ................................................................4-2

4.1.1.1 Compatibility Area...............................................................4-3

4.1.1.2 Extended Memory Area ......................................................4-4

4.1.1.3 AGP Memory Address Range.............................................4-5

4.1.1.4 AGP DRAM Graphics Aperture...........................................4-6

4.1.1.5 System Management Mode (SMM) Memory Range...........4-6

4.1.2 Memory Shadowing .........................................................................4-8

4.1.3 I/O Address Space...........................................................................4-8

4.1.4 AGP I/O Address Mapping...............................................................4-8

4.1.5 Decode Rules and Cross-Bridge Address Mapping ........................4-9

4.1.5.1 PCI Interface Decode Rules ...............................................4-9

4.1.5.2 AGP Interface Decode Rules ..............................................4-9

4.1.5.3 Legacy VGA Ranges ........................................................4-10

4.2 Host Interface..............................................................................................4-10

4.2.1 Host Bus Device Support...............................................................4-10

4.2.2 Symmetric Multiprocessor (SMP) Protocol Support.......................4-13

4.2.3 In-Order Queue Pipelining .............................................................4-13

4.2.4 Frame Buffer Memory Support (USWC) ........................................4-14

4.3 DRAM Interface ..........................................................................................4-14

4.3.1 DRAM Organization and Configuration..........................................4-14

4.3.1.1 Configuration Mechanism For DIMMS ..............................4-15

4.3.2 DRAM Address Translation and Decoding ....................................4-16

4.3.3 SDRAMC Register Programming ..................................................4-18

4.3.4 DRAMT Register Programming .....................................................4-19

4.3.5 SDRAM Paging Policy ...................................................................4-19

4.4 PCI Interface ...............................................................................................4-20

4.5 AGP Interface .............................................................................................4-20

4.6 Data Integrity Support .................................................................................4-20

4.6.0.1 Non-ECC (Default Mode of Operation) .............................4-20

4.6.1 CPU Bus Integrity ..........................................................................4-20

4.6.2 PCI Bus Integrity ............................................................................4-20

4.7 System Clocking .........................................................................................4-21

4.8 Power Management....................................................................................4-21

4.8.1 Overview ........................................................................................4-21

4.8.2 82443ZX Reset ..............................................................................4-23

4.8.2.1 CPU Reset ........................................................................4-24

4.8.2.2 CPU Clock Ratio Straps....................................................4-24

4.8.2.3 82443ZX Straps ................................................................4-24

4.8.3 Clock Control Functions .................................................................4-25

4.8.4 SDRAM Power Down Mode...........................................................4-25

4.8.5 SMRAM..........................................................................................4-25

5

Pinout and Package Information................................................................................5-1

5.1 82443ZX Pinout ............................................................................................5-1

5.2 Package Dimensions ....................................................................................5-8

82443ZX Host Bridge Datasheet

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