87C524 查看數據表（PDF） - Philips Electronics
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87C524 Datasheet PDF : 26 Pages
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Philips Semiconductors
80C51 8-bit microcontrollers
16K/32K, 512 OTP, I2C, watchdog timer
Product specification
87C524/87C528
PIN DESCRIPTIONS
PIN NO.
MNEMONIC DIP LCC QFP TYPE
NAME AND FUNCTION
VSS
VDD
P0.0–0.7
P1.0–P1.7
20
22
16
40
44
38
I Ground: circuit ground potential.
I Power Supply: +5 V power supply pin during normal operation, Idle mode and
Power-down mode.
39–32 43–36 37–30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to
them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory. In
this application, it uses strong internal pull-ups when emitting 1s.
1–8 2–9 40–44 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and P1.7
1–3
which have open drain. Port 1 pins that have 1s written to them are pulled high by the
internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled
low will source current because of the internal pull-ups. (See DC Electrical Characteristics:
IIL). Port 1 can sink/source one TTL (4 LSTTL) inputs. Port 1 receives the low-order
address byte during program memory verification. Port 1 also serves alternate functions for
timer 2:
1
2
40
I T2 (P1.0): Timer/counter 2 external count input (following edge triggered).
2
3
41
I T2EX (P1.1): Timer/counter 2 trigger input.
7
8
2
I/O SCL (P1.6): I2C serial port clock line.
8
9
3
I/O SDA (P1.7): I2C serial port data line.
P2.0–P2.7
21–28 24–31 18–25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have
1s written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 2 pins that are externally being pulled low will source current because of the
internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order
address byte during fetches from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it
uses strong internal pull-ups when emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function
register.
P3.0–P3.7
RST
ALE
PSEN
EA
XTAL1
XTAL2
10–17 11,
5,
13–19 7–13
10
11
5
11
13
7
12
14
8
13
15
9
14
16
10
15
17
11
16
18
12
17
19
13
9
10
4
30
33
27
29
32
26
31
35
29
19
21
15
18
20
14
I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have
1s written to them are pulled high by the internal pull-ups and can be used as inputs. As
inputs, port 3 pins that are externally being pulled low will source current because of the
pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of
the SC80C51 family, as listed below:
I RxD (P3.0): Serial input port
O TxD (P3.1): Serial output port
I INT0 (P3.2): External interrupt
I INT1 (P3.3): External interrupt
I T0 (P3.4): Timer 0 external input
I T1 (P3.5): Timer 1 external input
O WR (P3.6): External data memory write strobe
O RD (P3.7): External data memory read strobe
I/O Reset: A high on this pin for two machine cycles while the oscillator is running, resets the
device. An internal diffused resistor to VSS permits a power-on reset using only an external
capacitor to VDD. After a watchdog timer overflow, this pin is pulled high while the internal
reset signal is active.
I/O Address Latch Enable: Output pulse for latching the low byte of the address during an
access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency, and can be used for external timing or clocking. Note that one ALE
pulse is skipped during each access to external data memory.
O Program Store Enable: The read strobe to external program memory. When the device is
executing code from the external program memory, PSEN is activated twice each machine
cycle, except that two PSEN activations are skipped during each access to external data
memory. PSEN is not activated during fetches from internal program memory.
I External Access Enable: EA must be externally held low during RESET to enable the
device to fetch code from external program memory locations 0000H to 7FFFH. If EA is
held high during RESET, the device executes from internal program memory unless the
program counter contains an address greater than 7FFFH. EA is don’t care after RESET.
I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator
circuits.
O Crystal 2: Output from the inverting oscillator amplifier.
1999 Jul 23
6
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