A32200A-1PG256B 查看數據表（PDF） - Actel Corporation

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A32200A-1PG256B

HiRel FPGAs

Actel Corporation 

HiRel FPGAs

1200XL Timing Model*

Input Delays

Internal Delays

I/O Module

tINYL = 1.7 ns

Combinatorial

Logic Module

tIRD2 = 5.2 ns†

Predicted

Routing

Delays

Output Delays

I/O Module

DQ

G

tINH = 0.0 ns

tINSU = 0.4 ns

tINGL = 3.7 ns

ARRAY

CLOCKS

tCKH = 7.1 ns

FMAX = 110 MHz

FO = 256

tPD = 3.7 ns

tRD1 = 1.7 ns

tRD2 = 2.5 ns

tRD4 = 3.7 ns

tRD8 = 7.0 ns

Sequential

Logic Module

tDLH = 6.6 ns

I/O Module

tDLH = 6.6 ns

Combin-

atorial

Logic

included

in tSUD

tSU = 0.4 ns

tHD = 0.0 ns

DQ

tRD1 = 1.7 ns

DQ

G

tENHZ = 7.5 ns

tCO = 3.7 ns

tOUTH = 0.0 ns

tOUTSU = 0.4 ns

tGLH = 5.9 ns

tLCO = 10.7 ns (64 loads, pad-pad)

*Values shown for A1280XL–1 at worst-case military conditions.

† Input module predicted routing delay.

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