A32200A-1PG256B 查看數據表（PDF） - Actel Corporation

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生产厂家

A32200A-1PG256B

HiRel FPGAs

Actel Corporation 

Sequential Timing Characteristics

Flip-Flops and Latches (ACT 3)

D

Y

E

CLK

CLR

(Positive edge triggered)

HiRel FPGAs

D1

G, CLK

E

Q

CLR

tSUD

tHD

tWCLKA

tSUENA

tHENA

tCO

Note:

1. D represents all data functions involving A, B, and S for multiplexed flip-flops.

tA

tCLR

tWASYN

19

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