A32200DX-1PG208M 查看數據表（PDF） - Actel Corporation

零件编号

产品描述 (功能)

生产厂家

A32200DX-1PG208M

HiRel FPGAs

Actel Corporation 

Product Family Profile

Family

Device

Capacity

System Gates

Logic Gates

SRAM Bits

Logic Modules

S-Modules

C-Modules

Decode

Flip-Flops (maximum)

User I/Os (maximum)

Packages (by pin count)

CPGA

CQFP

Performance

System Speed (maximum)

ACT 2

A1240A A1280A

6,000

4,000

NA

684

348

336

NA

568

104

12,000

8,000

NA

1,232

624

608

NA

998

140

132

176

—

172

40 MHz 40 MHz

ACT 1

A1010B A1020B

1,800

1,200

NA

295

—

295

NA

147

57

3,000

2,000

NA

547

—

547

NA

273

69

84

84

—

84

20 MHz 20 MHz

High-Reliability, Low-Risk Solution

Actel builds the most reliable field programmable gate arrays

(FPGAs) in the industry, with overall antifuse reliability

ratings of less than 10 Failures-In-Time (FITs),

corresponding to a useful life of more than 40 years. Actel

FPGAs have been production proven, with more than five

million devices shipped and more than one trillion antifuses

manufactured. Actel devices are fully tested prior to

shipment, with an outgoing defect level of less than 100 ppm.

(Further reliability data is available in the Actel Device

Reliability Report, at http://www.actel.com/hirel).

Benefits

Minimized Cost Risk

With Actel’s line of development tools, designers can produce

as many chips as they choose for just the cost of the device

itself. There will be no NRE charges to cut into the

development budget each time a new design is tried.

Minimized Time Risk

After the design is entered, placement and routing is

automatic, and programming the device takes only about 5 to

15 minutes for an average design. Designers save time in the

design entry process by using tools with which they are

familiar.

Minimized Reliability Risk

The PLICE antifuse is a one-time programmable, nonvolatile

connection. Since Actel devices are permanently

programmed, no downloading from EPROM or SRAM storage

is required. Inadvertent erasure is impossible, and there is no

need to reload the program after power disruptions.

Fabrication using a low-power CMOS process means cooler

junction temperatures. Actel’s non-PLD architecture delivers

lower dynamic operating current. Our reliability tests show a

very low failure rate of 6.6 FITs at 90°C junction temperature

with no degradation in AC performance. Special stress testing

at wafer test eliminates infant mortalities prior to packaging.

Minimized Security Risk

Reverse engineering of programmed Actel devices from

optical or electrical data is extremely difficult. Programmed

antifuses cannot be identified from a photograph or by using

an SEM. The antifuse map cannot be deciphered either

electrically or by microprobing. Each device has a silicon

signature that identifies its origins, down to the wafer lot and

fabrication facility.

Minimized Testing Risk

Unprogrammed Actel parts are extensively tested at the

factory. Routing tracks, logic modules, and programming,

debug and test circuits are 100 percent tested before

shipment. AC performance is ensured by special speed path

tests, and programming circuitry is verified on test antifuses.

During the programming process, an algorithm is run to

ensure that all antifuses are correctly programmed. In

addition, Actel’s Silicon Explorer diagnostic tool uses

ActionProbe circuitry, allowing 100 percent observability of

all internal nodes to check and debug the design.

Actel FPGA Description

The Actel families of FPGAs offer a variety of packages,

speed/performance characteristics, and processing levels for

use in all high reliability and military applications. Devices

are implemented in a silicon gate, two-level metal CMOS

process, utilizing Actel’s PLICE antifuse technology. This

2

Share Link: