A4984 查看數據表（PDF） - Allegro MicroSystems

零件编号

产品描述 (功能)

生产厂家

A4984

DMOS Microstepping Driver with Translator And Overcurrent Protection

Allegro MicroSystems 

A4984

DMOS Microstepping Driver with Translator

And Overcurrent Protection

specifications.

Enable Input (¯E¯¯N¯¯A¯¯B¯¯L¯¯E¯). This input turns on or off all of the

FET outputs. When set to a logic high, the outputs are disabled.

When set to a logic low, the internal control enables the outputs

as required. The translator inputs STEP, DIR, and MSx, as well as

the internal sequencing logic, all remain active, independent of the

¯E¯¯N¯¯A¯¯B¯¯L¯¯E¯ input state.

Shutdown. In the event of a fault, overtemperature (excess TJ)

or an undervoltage (on VCP), the FET outputs of the A4984 are

disabled until the fault condition is removed. At power-on, the

UVLO (undervoltage lockout) circuit disables the FET outputs

and resets the translator to the Home state.

Sleep Mode ( ¯S¯¯L¯¯E¯¯E¯¯P¯ ). To minimize power consumption

when the motor is not in use, this input disables much of the

internal circuitry including the output FETs, current regulator,

and charge pump. A logic low on the S¯¯L¯¯E¯¯E¯¯P pin puts the A4984

into Sleep mode. A logic high allows normal operation, as well as

start-up (at which time the A4984 drives the motor to the Home

microstep position). When emerging from Sleep mode, in order

to allow the charge pump to stabilize, provide a delay of 1 ms

before issuing a Step command.

Mixed Decay Operation. The bridge can operate in Mixed

Decay mode, depending on the step sequence, as shown in fig-

ures 8 through 11. As the trip point is reached, the A4984 initially

goes into a fast decay mode for 31.25% of the off-time, tOFF.

After that, it switches to Slow Decay mode for the remainder of

tOFF. A timing diagram for this feature appears in figure 7.

Synchronous Rectification. When a PWM-off cycle is

triggered by an internal fixed-off time cycle, load current recircu-

lates according to the decay mode selected by the control logic.

This synchronous rectification feature turns on the appropriate

FETs during current decay, and effectively shorts out the body

diodes with the low FET RDS(ON). This reduces power dissipation

significantly, and can eliminate the need for external Schottky

diodes in many applications. Synchronous rectification turns off

when the load current approaches zero (0 A), preventing reversal

of the load current.

5 A / div.

Fault

latched

t→

Figure 4. Short-to-ground event

5 A / div.

Fixed off-time

t→

Figure 5. Shorted load (OUTxA → OUTxB) in

Slow decay mode

5 A / div.

Fixed off-time

Fast decay portion

(direction change)

t→

Figure 6. Shorted load (OUTxA → OUTxB) in

Mixed decay mode

Allegro MicroSystems, Inc.

10

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

Share Link: