AAT1162 查看數據表（PDF） - Analog Technology Inc

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AAT1162

Voltage-Scaling Step-Down Converter

Analog Technology Inc 

AAT1162

12V, 1.5A Step-Down DC/DC Converter

Pin Descriptions

Pin #

1, 2, EP2

3, 12

4, 5

6, 13,

14, EP1

7

8

9

10

11

15

16

Symbol

LX

N/C

IN

DGND

AIN

LDO

FB

COMP

AGND

EN

PGND

Function

Power switching node. LX is the drain of the internal P-channel switch and N-channel syn-

chronous rectifier. Connect the output inductor to the two LX pins and to EP2. A large

exposed copper pad under the package should be used for EP2.

Not connected.

Power source input. Connect IN to the input power source. Bypass IN to DGND with a

22µF or greater capacitor. Connect both IN pins together as close to the IC as possible. An

additional 100nF ceramic capacitor should also be connected between the two IN pins and

DGND, pin 6

Exposed Pad 1 Digital Ground, DGND. The exposed thermal pad (EP1) should be connected

to board ground plane and pins 6, 13, and 14. The ground plane should include a large

exposed copper pad under the package for thermal dissipation (see package outline).

Internal analog bias input. AIN supplies internal power to the AAT1162. Connect AIN to the

input source voltage and bypass to AGND with a 0.1µF or greater capacitor. For additional

noise rejection, connect to the input power source through a 10Ω or lower value resistor.

Internal LDO bypass node. The output voltage of the internal LDO is bypassed at LDO. The

internal circuitry of the AAT1162 is powered from LDO. Do not draw external power from LDO.

Bypass LDO to AGND with a 1µF or greater capacitor.

Output voltage feedback input. FB senses the output voltage for regulation control. For fixed

output versions, connect FB to the output voltage. For adjustable versions, drive FB from the

output voltage through a resistive voltage divider. The FB regulation threshold is 0.6V.

Control compensation node. Connect a series RC network from COMP to AGND, R = 51k

and C = 270pF.

Analog signal ground. Connect AGND to PGND at a single point as close to the IC as possible.

Active high enable input. Drive EN high to turn on the AAT1162; drive it low to turn it off. For

automatic startup, connect EN to IN through a 4.7kΩ resistor. EN must be biased high, biased

low, or driven to a logic level by an external source. Do not let the EN pin float when the

device is powered.

Power ground. Connect AGND to PGND at a single point as close to the IC as possible.

Pin Configuration

TDFN34-16

(Top View)

LX 1

LX 2

N/C 3

IN 4

IN 5

DGND 6

AIN 7

LDO 8

EP2

EP1

16 PGND

15 EN

14 DGND

13 DGND

12 N/C

11 AGND

10 COMP

9 FB

2

1162.2007.09.1.2

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