AAT3114A 查看數據表（PDF） - Analog Technology Inc

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AAT3114A

High Efficiency 1.5X Fractional Charge Pumps For White LED Applications

Analog Technology Inc 

PRODUCT DATASHEET

AAT3113, AAT3114/14A

ChargePumpTM High Efficiency 1.5X Fractional Charge Pumps For White LED Applications

Functional Block Diagram

VIN

Soft Start

600kHz

Oscillator

Voltage

Reference

1.5X

Charge

Pump

C1+

C1-

C2+

C2-

OUT

EN/SET

S2Cwire

Interface

5

32x8 bit

ROM

8

Current

Mode

DAC

D1

D2

D3

D4

D5*

D6*

GND

* AAT3114/14A only

Functional Description

The AAT3113 and AAT3114/14A devices are high effi-

ciency 1.5X fractional charge pumps intended for white

LED backlight applications. The fractional charge pump

consists of a linear regulator followed by a 1.5X charge

pump. The AAT3113 and AAT3114/14A require only four

external components: two 1µF ceramic capacitors for the

charge pump flying capacitors (C1 and C2), one 1µF

ceramic capacitor for CIN, and one 0.33µF to 1µF ceram-

ic capacitor for COUT. The charge pump output is con-

verted into four or six constant current outputs (D1 to

D4 or D6) to drive four or six individual LEDs with a

maximum of 20mA each. The current source output

magnitude is controlled by the EN/SET serial data

S2Cwire interface. The interface records rising edges of

the EN/SET pin and decodes them into 32 individual cur-

rent level settings each 1dB apart (see Table 1, Current

Level Settings). Code 32 is full scale, and Code 1 is full

scale attenuated by 31dB. The modulo 32 interface

wraps states back to state 1 after the 32nd clock. With

each EN/SET pulse, the output current increases by 1dB.

To decrease the output current by 1dB, 31 EN/SET clock

pulses are required. The counter can be clocked at

speeds up to 1MHz, so intermediate states are not visi-

ble. The first rising edge of EN/SET enables the IC and

initially sets the output LED current to -31dB, the lowest

setting equal to 525µA. Once the final clock cycle is input

for the desired brightness level, the EN/SET pin is held

high to maintain the device output current at the pro-

grammed level. The device is disabled 500µs after the

EN/SET pin transitions to a logic low state.

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