ACPL-796J-000E 查看數據表（PDF） - Avago Technologies
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ACPL-796J-000E Datasheet PDF : 16 Pages
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Table 8. Timing Specifications
Unless otherwise noted, TA = –40°C to +105°C, VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V.
Parameter
Symbol Min. Typ. Max. Units Test Conditions/Notes
Fig.
Modulator Clock Input Frequency fMCLKIN 5
Data Delay After Rising Edge of
tD
3
MCLKIN[1]
10
20
MHz Clock duty cycle 40% to 60%
15
ns
CL = 15 pF
5
Notes:
1. Data changes at the clock rising edge so it can be safely read at the falling edge, although it can be read at the rising edge if preferred.
2. When VDD1 is not supplied, MDAT is high ie modulator output level is “1”
MCLKIN
tD
MDAT
Figure 5. Data timing.
Table 9. Package Characteristics
Parameter
Symbol Min. Typ. Max. Units Test Conditions
Note
Input-Output Momentary
Withstand Voltage
Input-Output Resistance
VISO
5000
RI-O
1012 1013
1011
Vrms RH ≤ 50%, t = 1 min;
1, 2
TA = 25°C
VI-O = 500 Vdc
2
TA = 100°C
2
Input-Output Capacitance
CI-O
1.4
pF
f = 1 MHz
2
Input IC Junction-to-Ambient
JAI
Thermal Resistance
83
°C/W 1 oz. trace, 2-layer PCB,
3
still air, TA = 25°C
Output IC Junction-to- Ambient
JAO
Thermal Resistance
85
°C/W 1 oz. trace, 2-layer PCB,
3
still air, TA = 25°C
Notes:
1. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 6000 Vrms for 1 second. This test is performed
before the 100% production test for partial discharge (method b) shown in IEC/EN/DIN EN 60747-5-5 Insulation Characteristic Table.
2. This is a two-terminal measurement: pins 1-8 are shorted together and pins 9-16 are shorted together.
3. Maximum power dissipation in analog side and digital side IC’s needs to be limited to ensure that their respective junction temperature is less than
125°C. The maximum permissible power dissipation is dependent on the thermal impedance and the ambient temperature.
7
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